Clarify multiple DMs/harts

Add hit bit to hardware triggers.

Confusing for everyone...

Added \Rnextdm to allow a debugger to discover multipled DMs, if they
exist.

Clarify what happens when \Fauthenticated is clear

Proposed solution to Issue #222

Fix link to pre-built pdf

Python interpreter to be used should default to Python2

Fixes #219

This allows the debugger to determine which hardware trigger was hit.

Fixes Issue #215.

Move Reg Access Abbrev table after sample register

Fixes issue #141.

It seems to fix Issue #196, and also gives us headers on every new page.

Abstract Command data usage depends on the command

It doesn't just depend on XLEN, because RV32 can still have 64-bit FPRs.
This change is backwards compatible.

Get rid of sbsingleread in favor of sbreadonaddr

Make \Fhaltsel WARL.

This is instead of using language that would allow this implementation,
but might be confusing about other implementations.

The problem is as follows:
1. Debugger writes to sbdata0, triggering a write.
2. Debugger writes to sbdata0 while the access is still in progress. A
busy error needs to be set.
3. The original access finishes with eg. an alignment error.

Before this change, we would have to pick which error (alignment/busy)
to report, while for full understanding the debugger needs to know both.
This is fixed by adding a sbbusyerror bit, which is used to indicate
busy errors, leaving sberror for other error reporting.

Re-apply e698a500 . No need to list out all the consecutive registers.

RISC-V ISA specs consciously never mentions caches.