The main difference is to remove the halt region in favor of 4
registers. This is slightly slower to determine which hart is halted if
their number is between 32 and 1024, but it allows for many more harts
overall, and the time to figure out which one is halted is O(log(N)).

Abstract Command data usage depends on the command

It doesn't just depend on XLEN, because RV32 can still have 64-bit FPRs.
This change is backwards compatible.

Get rid of sbsingleread in favor of sbreadonaddr

Make \Fhaltsel WARL.

This is instead of using language that would allow this implementation,
but might be confusing about other implementations.

The problem is as follows:
1. Debugger writes to sbdata0, triggering a write.
2. Debugger writes to sbdata0 while the access is still in progress. A
busy error needs to be set.
3. The original access finishes with eg. an alignment error.

Before this change, we would have to pick which error (alignment/busy)
to report, while for full understanding the debugger needs to know both.
This is fixed by adding a sbbusyerror bit, which is used to indicate
busy errors, leaving sberror for other error reporting.

Re-apply e698a500 . No need to list out all the consecutive registers.

RISC-V ISA specs consciously never mentions caches.

LaTeX is terrible, but not as terrible as everything else. :-(

Fixes issue #210.

The big change is that we get rid of the stale concept, using \Fsbbusy
instead.

Remove H bits from triggers.

H mode doesn't exist anymore.

sbaddress0 writes trigger reads if sbreadonaddr is set.

Remove dmerr

Issue #192

Issue #184.

dret: Legal only in Debug Mode

Explicitly list data[1-10] and progbuf[1-15]