Fixes #618

* Fix #587

* Traps caused by triggers can be delegated below M mode like all other traps.

* Divide the spec into ISA and non-ISA.

There are separate definition-of-done requirements for ISA vs. non-ISA
specs. Our spec contains both, so clearly mark what is what.

* Define ISA/non-ISA.

* Further diagram update.

Hopefully addresses #631 and make it more exhaustive.

* Add more detail.

Added reset states, more halt causes, and a few other cleanups.

* Fix #587

* Fix #630

* Fix typo

* Update Run/Halt Debug State Machine.

Bring the diagram up-to-date with what the spec says. Added abstract
command error states when an abstract command is issued while running.
Removed individual abstract commands since it got to be too messy.

In response to thread on mailing list subject:"A query regarding the
State Machine".

* Refine diagram a bit.

* Note that the diagram is not exhaustive.

* Fix #587

* Describe vs and vu fields consistently with others in etrigger/itrigger.
hcontext is also writable outside M mode.

There is currently no latest draft. Fixes #626.

* Fix #587

* Clarify abstractauto per https://lists.riscv.org/g/tech-debug/message/413

* Fix #587

* Clarify for https://lists.riscv.org/g/tech-debug/message/377

* Fix #587

* Fix typos

In a pipelined core, executing an instruction takes multiple cycles. It is also possible for an instruction to be executed but not committed or executed out-of-order with respect to the preceding/succeeding instruction.  The 'timing' bit description as written appears to exclude pipelining, speculation, and out-of-order execution.

Changed 'executed' to 'committed' three times each in 'timing' description of MCONTROL and MCONTROL6 registers.

* Fix #587

* Clarify aarpostincrement wrapping
See https://lists.riscv.org/g/tech-debug/message/339

* Change wording per PR review comments

* Fix #587

* hasel is WARL since it may be tied off
hartsel is WARL because not all bits have to be implemented

* Define some more terms/acronyms.

Many acronymos contributed by Bruce Ableidinger.

* CSR = Control and Status Register

Co-authored-by: Paul Donahue <48959409+pdonahue-ventana@users.noreply.github.com>

* IR = JTAG IR

Co-authored-by: Megan Wachs <megan@sifive.com>

* DR = JTAG DR

Co-authored-by: Megan Wachs <megan@sifive.com>

* XLEN is hart-specific

Co-authored-by: Megan Wachs <megan@sifive.com>

* Clarify virtual address

Co-authored-by: Megan Wachs <megan@sifive.com>

* Review feedback.

Removed a bunch of terminology entries, and clarified several others.

* Add TM.

* Slight tweaks based on review.

* Use "hardware platform" consistently.

I hope.

* Simpler language

Co-authored-by: Paul Donahue <48959409+pdonahue-ventana@users.noreply.github.com>

* Alphabetize list.

Co-authored-by: Paul Donahue <48959409+pdonahue-ventana@users.noreply.github.com>
Co-authored-by: Megan Wachs <megan@sifive.com>

Suggested by Ken Dockser, since dret has no meaning outside specific
implementations.

This is also what the privileged spec does.

* Clarify details around fence and progbuf.

Addresses #533.

* Fix typo.

Co-authored-by: Ernie Edgar <43148441+ernie-sifive@users.noreply.github.com>

* "output," not "I/O"

* Remove all mentions of fence.

I was going to move this into the appendix, but I realize I don't even
understand why it needs to be mentioned there.

* Mention fence in appendix

Co-authored-by: Ernie Edgar <43148441+ernie-sifive@users.noreply.github.com>

* Rephrase.

I think this says the same thing, but more concisely.

* Give example of side effect we need the fence for.

Co-authored-by: Ernie Edgar <43148441+ernie-sifive@users.noreply.github.com>

* Clarify how many bits mcontrol/mcontrol6 compare.

Addresses #569.

* Address the easy feedback.

* Clarify that trigger values are always 0-extended.

* Hopefully make things less ambiguous.

Which is, unfortunately, not the same as making them more clear.

* Minor rephrase.

maskmax=0 means match=1 is not supported.
There must be at least one 0 bit in the tdata2 when using match=1.

Addresses #586.

Addresses #582.

Addresses part of #565.

* Add version 1.0 value to dtmcs.version field

* Use dtmcs.version value 1 for both 0.13 and 1.0

Excluding clarifications, which don't change the spec.

* Add clic bit to tmexttrigger.

Addresses #412.

* Don't limit to CLIC.

Co-authored-by: Paul Donahue <48959409+pdonahue-ventana@users.noreply.github.com>

* clic -> intctl

Co-authored-by: Paul Donahue <48959409+pdonahue-ventana@users.noreply.github.com>

* Explain how to simply write any trigger.

Addresses #573.

This new requirement only changes hardware with writable types. Even
there it is trivial to implement as long as types 2 or 6 are supported,
and those types become selected when 0 is written.

* Fix typo.

Co-authored-by: Ernie Edgar <43148441+ernie-sifive@users.noreply.github.com>

Co-authored-by: Ernie Edgar <43148441+ernie-sifive@users.noreply.github.com>

* Clarify trigger CSR behavior when XLEN changes.

Addresses #583.

* 32-bit writes clear inaccessible bits.

* Writes to *registers* clear inaccessible bits.

* add dmstatus.ndmresetpending

* add dmstatus.ndmresetpending

* Apply suggestions from code review

Co-authored-by: Tim Newsome <tim@sifive.com>

* Apply suggestions from code review

Co-authored-by: Benjamin Staveley <bstaveley@ventanamicro.com>
Co-authored-by: Tim Newsome <tim@sifive.com>

Addresses #572.