This fixes a bug introduced in #506.

See e-mail: https://lists.riscv.org/g/tech-debug/topic/99398782#1291

Clarify trap in progbuf behavior.

Clarify when hit0/hit1 are updated by TM.

Allow partial register updates for instructions that already do that.

Based on lots of mailing list discussion:
https://lists.riscv.org/g/tech-debug/topic/98622044#1178

D-Mode exceptions may modify DPC

Because the definition of DPC already says "Executing the Program Buffer
may cause the value of dpc to become unspecified."

This fixes a contradiction in the spec.

Don't say master/slave

bus master -> bus coordinator
bus slave -> bus subordinate device

Addresses #844.

Clarify that icount decrements on interrupt traps.

The rationale is that if icount is enabled in the current mode and the
mode of the trap handler, when you single step you don't want to step
past the first instruction of the trap handler, which you didn't know
was going to be executed. Having to step multiple times to get past an
interrupt to actually execute the instruction you tended to step is
addressed the same way as already documented in the appendix.

Addresses a question from #842.

Addresses #840.

Reentrant trigger prevention inhibits match *or fire*

This is a substantive change, but a bugfix, so OK to merge.

Addresses #812.

* Add inst, reg, and field macros.

To help consistently format instructions, register names, and field
names.

* Describe how CMO instructions match triggers.

See e-mail subject:"Sdtrig and CMO".

* Rephrasing again.

* Refine language.

* Triggers only match CMOs when size=0 and select=0.

Address must be base address or the passed address, but should be the
address of every address in the affected cache lines.

* Rephrase CMO address comparison.

Refer to "virtual address covered by any of the affected cache lines."

* Rephrase CMO trigger compare values again.

* Rephrase which addresses are compare values for CMOs.

* Don't try to account for virtual address aliasing.

Last build was slightly out of date somehow.

Clarify that stepie applies to dcsr.step but not icount.

Clarify action 8/9 signal TM external triggers.

Also be more consistent in using "TM external triggers" in definition of
tmexttrigger.

Addresses #783

Rename dtmc.dmihardreset field to dtmhardreset

Addresses #470.

Document native single step options.

* Remove references to the timing bit.
Fixes #827.  Also changed trigger examples to fix some bugs, add
the type field, add vs/vu in some examples, enhance one example
to include textra, etc.

* Review feedback

Co-authored-by: Tim Newsome <tim@sifive.com>
Signed-off-by: Paul Donahue <48959409+pdonahue-ventana@users.noreply.github.com>

* Apply suggestions from code review

Co-authored-by: Tim Newsome <tim@sifive.com>
Signed-off-by: Paul Donahue <48959409+pdonahue-ventana@users.noreply.github.com>

---------

Signed-off-by: Paul Donahue <48959409+pdonahue-ventana@users.noreply.github.com>
Co-authored-by: Tim Newsome <tim@sifive.com>

Now include both mechanisms suggested for native triggers in
single-privilege-mode systems, instead of just carefully counting
instruction.

Addresses #830.

---
Improve single step description for different debug features

This commit updates the description of single step implementation in the
debugger_implementation.tex file. It now provides a more detailed and clear
explanation on how to single step through code running in the same privilege
mode as the debugger, depending on the availability of \FcsrTcontrolMpte,
\FcsrTcontrolMte, and automatically preventing \FcsrMcontrolSixAction=0 triggers
from matching when entering a trap handler.
(gpt-4)

textra inhibits firing in addition to matching.

icount: Remove confusing statement about inhibited trigger.

"Inhibited" is not well-defined, and this language is no longer
necessary. It was added when the original sentence said:
> When \FcsrIcountCount is greater than 1, every instruction completed or
> trap taken from a mode where the trigger is enabled decrements
> \FcsrIcountCount by 1.

Now there is no more reference to a mode, so the clarification isn't
needed either.

Addresses #813

Document behavior for abstract dpc access while running.

Those two are distinct in the case of icount, where pending becomes set
on match, and firing happens later. We want to make sure not to fire in
a place where match is disallowed.

Addresses #812.

Addresses #824.

Clarify mode that dret returns to

Describe what happens on halt.

This way I have a place to describe what happens with vector
instructions.

Hopefully also answers part of #822.

Clarify that dmi.op describe dmi.address contents.

Maybe would have avoided #819.

Document trigger behavior with vector/push/pop accesses.