Feedback:
> Attempts to access a non-existent Core Debug Register now raise an
> illegal instruction exception.  This is inconsistent with general RISC-V
> practice of not mandating, for example, trapping of reserved and
> unimplemented opcodes and CSRs.  This practice is partially to allow
> implementation flexibility to not bear the cost of decoding, but most
> notably to allow for backward compatibility.  Otherwise a future design
> implementing a future debug extension that changes a reserved register
> into a defined/implemented register would not be backward compatible
> with this spec - which mandates that the register must trap.
> But instead a non-normative recommendation to trap would be appropriate.

The privspec says "Attempts to access a non-existent CSR raise an
illegal instruction exception" but "The ARC has recognized this error
earlier this year and intends to correct (i.e. loosen) it in Priv 1.13."

This change was originally introduced to deal with tinfo and enumerating
trigger registers, and also to be consistent with the privspec. See
https://lists.riscv.org/g/tech-debug/topic/95589931

* Program Buffer: Clarify requirements for case progbufsize==1

- Clarified that both the listed requirements apply only to
the case of progbufsize==1, as discussed in
https://github.com/riscv/riscv-debug-spec/issues/863



- Minor reword and simplification of the sentences

- Changed the order of paragraphs so that:
  - Generic requirements are stated first (Debug Mode, cmderr, ...)
  - Special requirements for progbufsize==1 are mentioned later

* Reflected review findings

---------

Co-authored-by: Jan Matyas <jan.matyas@codasip.com>

Update chapter names per ARC review feedback

AR: Use manager/subordinate for master/slave.

Fix typo in execution appendix: execute -> postexec

Address AR feedback:
> Master/slave terminology is obviously being replaced across RV specs -
> in a somewhat haphazard manner as far as what is being used for
> replacements.  The ARC suggests using the following (and will be
> proposing this to be the standard replacement across RV specs):
> Manager/subordinate  (which remains intuitive and happens to maintain
> the M/S starting letters fwiw)

Fixes #859.

In Debug Mode, triggers don't match or fire.

The existing language implied that hit bits would be updated, which
doesn't make any sense. That's because that line was written before we
had hit bits.

Clarifies #851.

* wrs.sto/nto act as nop in debug mode; follow wfi

* wrs.sto/nto behavior when halt requested; follow wfi

* behavior of stepping over wrs.sto/nto; follow wfi

* formulate wfi/wrs restrictions as a rule

* formulate single step over wrs/wfi as a rule

External trigger signals inputs don't cause trigger output.

This fixes a bug introduced in #506.

See e-mail: https://lists.riscv.org/g/tech-debug/topic/99398782#1291

Add dtmcs.errinfo.

This gives more information about what exactly went wrong, when a DMI
access fails.

This is certainly a substantive (albeit backwards compatible) change.
Can it go into 1.0?

Clarify trap in progbuf behavior.

Clarify when hit0/hit1 are updated by TM.

Allow partial register updates for instructions that already do that.

Based on lots of mailing list discussion:
https://lists.riscv.org/g/tech-debug/topic/98622044#1178

D-Mode exceptions may modify DPC

Because the definition of DPC already says "Executing the Program Buffer
may cause the value of dpc to become unspecified."

This fixes a contradiction in the spec.

Don't say master/slave

bus master -> bus coordinator
bus slave -> bus subordinate device

Addresses #844.

Clarify that icount decrements on interrupt traps.

The rationale is that if icount is enabled in the current mode and the
mode of the trap handler, when you single step you don't want to step
past the first instruction of the trap handler, which you didn't know
was going to be executed. Having to step multiple times to get past an
interrupt to actually execute the instruction you tended to step is
addressed the same way as already documented in the appendix.

Addresses a question from #842.

Addresses #840.

Reentrant trigger prevention inhibits match *or fire*

This is a substantive change, but a bugfix, so OK to merge.

Addresses #812.

* Add inst, reg, and field macros.

To help consistently format instructions, register names, and field
names.

* Describe how CMO instructions match triggers.

See e-mail subject:"Sdtrig and CMO".

* Rephrasing again.

* Refine language.

* Triggers only match CMOs when size=0 and select=0.

Address must be base address or the passed address, but should be the
address of every address in the affected cache lines.

* Rephrase CMO address comparison.

Refer to "virtual address covered by any of the affected cache lines."

* Rephrase CMO trigger compare values again.

* Rephrase which addresses are compare values for CMOs.

* Don't try to account for virtual address aliasing.

Last build was slightly out of date somehow.

Clarify that stepie applies to dcsr.step but not icount.

Clarify action 8/9 signal TM external triggers.

Also be more consistent in using "TM external triggers" in definition of
tmexttrigger.

Addresses #783

Rename dtmc.dmihardreset field to dtmhardreset

Addresses #470.