- Aug 03, 2018
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Tim Newsome authored
Fixes #313.
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Tim Newsome authored
Fixes #317.
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- Jul 21, 2018
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Tim Newsome authored
Fixes #312.
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- Jul 20, 2018
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Tim Newsome authored
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- Jul 19, 2018
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Tim Newsome authored
This resolves problems when matching against instructions that aren't MXLEN bits wide, and allows matches against data accesses of specific sizes.
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- Jul 17, 2018
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Tim Newsome authored
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- Jul 13, 2018
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Tim Newsome authored
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- Jul 10, 2018
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Tim Newsome authored
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Tim Newsome authored
* datacount cannot be 0 It must be at least 1 so GPRs can be accessed. * Clarify minimum \Fdatacount for RVxx * Move \Fdatacount details to commentary.
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- Jul 07, 2018
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Tim Newsome authored
* Clarifications requested by Jeremy Bennett * Targets don't have to implement access to all regs
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Tim Newsome authored
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Tim Newsome authored
* Clarify that trigger registers are WARL. * Clarify what a trigger chain is and when it fires. * Incorporate feedback.
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Tim Newsome authored
Previously it was confusing that especially Table 3.8 would end up in the dmstatus Section. #300
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Tim Newsome authored
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- Jul 04, 2018
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Tim Newsome authored
* Completing progbuf exec is I/O for fence insts. We need something like this so a debugger can ensure a memory change is propagated to all harts in a system. * Completing progbuf is just output Also explain how this might work in an execution-based implementation.
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- Jun 27, 2018
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Tim Newsome authored
* Add uncached to abstract access memory. Requested by Thomas Wicki, and seems straightforward enough. * \Funcached is optional. * Slight rephrasing. * It's OK to implement "partial commands." * Replace no-program-buffer example with no-csr * Make "uncached" bit simply "target-specific."
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- Jun 20, 2018
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Tim Newsome authored
* Only write busy to \Fcmderr if \Fcmderr is 0. * Be a bit more precise. * Only look at \Fcmderr when \Fbusy is 0 Also suggest how to deal with failures after sending a burst of commands. * Incorporate feedback.
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- Jun 17, 2018
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Tim Newsome authored
It's been a while. I haven't been committing the PDF with every PR because the conflicts are a pain.
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Tim Newsome authored
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Tim Newsome authored
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- Jun 15, 2018
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Tim Newsome authored
This reverts commit 7c66968e.
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Tim Newsome authored
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- Jun 09, 2018
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Tim Newsome authored
* Add Access Memory abstract command Source provided by Thomas Wicki * Add autoincrement to abstract memory access Also added examples in the debugger implementation section. * Thomas requested Robert get credit for this idea. * Incorporate review back, add aamvirtual bit Removed transfer and postexecute bits from abstract memory access. Renamed a few fields to avoid confusion. Add aamvirtual bit to abstract memory access. * Fix memory references to include abstract command * Fix typo.
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Tim Newsome authored
* Specify an Exception Trigger I tried to get all the sources from the Syntacore proposal in, but did not add the various timing options. We do get interrupt sources now as well as the exception sources. * Redo etrigger. Now we support every source that's explicitly mentioned in the mcause definition in the privspec. Also make a separate table for \Faction instead of repeating its definition over and over. * Allow more interrupts/causes to be triggered on. Clarified use of \Faction a bit as well. * Incorporate review feedback. * Attempt to clarify u/s/m * Break exception trigger into two triggers. This avoids using tdata3, which helps with certain implementations where trigger types are writable. * Rebuild pdf.
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- Jun 06, 2018
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Tim Newsome authored
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- Jun 04, 2018
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Tim Newsome authored
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- May 31, 2018
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Tim Newsome authored
* Make trigger types writable. This gives a hardware more options when implementing triggers. Instead of requiring separate triggers for separate types, they could opt to reuse the configuration storage. * Unimplemented tinfo traps, doesn't read 0. * Update detection algorithm for previous commit
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- May 30, 2018
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Tim Newsome authored
* Explain priority assignment rationale. Issue #276. * Make cause priorities suggested.
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- May 26, 2018
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Tim Newsome authored
This fixes a corner case when chaining triggers, #275.
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- May 23, 2018
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Tim Newsome authored
* Reading tselect doesn't guarantee a valid trigger. * Clarify algorithm to enumerate triggers. * Reword debuggers reading back tselect.
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- May 22, 2018
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Megan Wachs authored
resethaltreq: Proposal for forcing a hart into debug mode out of reset
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- May 21, 2018
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Megan Wachs authored
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Megan Wachs authored
resethaltreq: add a bit to dmstatus to indicate whether this functionality is present resethaltreq: Modify the proposal to have set/clear bits resethaltreq: correct some usages of debugger->Debug Module
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- May 17, 2018
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Tim Newsome authored
Issue #264.
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- May 05, 2018
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Megan Wachs authored
mprven: Add a bit to enable MPRV to take effect in debug mode
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- May 04, 2018
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mwachs5 authored
MPRVEN: minor text edits
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Megan Wachs authored
Appendix: correct & clarify what debugger/DM do
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Megan Wachs authored
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Megan Wachs authored
Remove merge commits from the changelog
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Tim Newsome authored
* Debuggers must not write sbcs while sbbusy is set Issue #258 * Grammar.
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