Change dcsr.prv reset value to 3

This will help avoid a trap where an implementation might end up with
prv 0 when entering debug out of reset. Even in that case prv should be
set from the privilege mode of the processor, which should be machine
mode, but specifying this as the actual value makes things a little
simpler.

Be more precise about core vs hart

Also fixes #226.

Be more precise about processor vs hart

Fixes #226

Clarify user responsibilities when debugging lr/sc

Modification of > 1024 hart proposal, maintains backwards compatibility

Clarify multiple DMs/harts

Fixes #228.

Add hit bit to hardware triggers.

Confusing for everyone...

Added \Rnextdm to allow a debugger to discover multipled DMs, if they
exist.

Clarify what happens when \Fauthenticated is clear

Proposed solution to Issue #222

Fix link to pre-built pdf

Python interpreter to be used should default to Python2

Fixes #219

This allows the debugger to determine which hardware trigger was hit.

Fixes Issue #215.

Move Reg Access Abbrev table after sample register

Fixes issue #141.

It seems to fix Issue #196, and also gives us headers on every new page.