See e-mail discussion subject:"Size for address trigger matching and
vector"

Refactor AMO discussion.

Now it's only in one place, instead of duplicated for mcontrol and
mcontrol6.

Reinstate timing

Harts/triggers belong to exactly one halt/resume group.

Clarify icount decrements on instruction execution

This reverts commit 91b7ae65.

I still think this should happen, but it needs to be backwards
compatible. Discussion on how to do this is ongoing, and I don't want
someone to grab the current spec and then not implement timing at all.

Hopefully clarify #799.

Suggest debugger behavior when icount stepping over restarting instruction

Tons of mailing list discussion, e.g. https://lists.riscv.org/g/tech-debug/message/1016

* Clarify JTAG connector section.

Make it more clear that MIPI-10 should be sufficient for everyone,
mostly by clearly putting MIPI-20 into an alternate connector section.

Expand just a tiny bit on cJTAG.

Update MIPI references to the current version of that document, and
mention the pinouts using the same names used there.

* Clarify what nTRST is for.

* Clearly label MIPI-10 as the Recommended JTAG Connector.

* more esoteric signals -> legacy JTAG signals

* nRESET is open drain.

* Unnecessary pins may be left unconnected

* Describe EXT pin.

* RTCK and TRIGOUT should be GND if not used.

* Clarify that nTRST_PD and RTCK are undesirable.

Reorganize the trigger signal table into Essential, Recommended,
Advanced, Specialized, and Legacy signals.

Expand mcontrol6.hit into hit0 and hit1, and remove mcontrol6.timing.

This was an awkward way to let the hardware know what it supports, and
it breaks down with load before triggers and AMOs. 2-bit hit is a much
better solution.

This simplifies a bunch of language, too, and makes it more clear that
timing is best-effort.

This lets an implementation be more specific about when a trigger fired
in relation to the instruction that matched, to avoid user confusion
when triggers fire late.

Previously we said "completes" which is not well defined. Also be clear
that xRET instructions count.

Make it clear that the trigger matches at most once per instruction.

Make capitalization more consistent.

I accidentally pushed the wrong branch, and then botched reverting.
Hopefully this is right.

This reverts commit 98bebe30.

The privileged spec already requires this.

This addresses a mailing list discussion subject:Clarification of enumeration procedure in Sdtrig ISA extension

* Explicitly allow debug mode to access debug mode CSRs for #772.

* Simpler way to address #772 while avoiding unintended consequences.

From discussion in #550.

Fixes #787.

* Clarify the term "trap" in execution-based implementations.

* Clarification from review

Co-authored-by: Tim Newsome <tim@sifive.com>
Signed-off-by: Paul Donahue <48959409+pdonahue-ventana@users.noreply.github.com>

Signed-off-by: Paul Donahue <48959409+pdonahue-ventana@users.noreply.github.com>
Co-authored-by: Paul Donahue <paul@pauldonahue.com>
Co-authored-by: Tim Newsome <tim@sifive.com>

Looks like Ubuntu jammy has the bugfix described in
https://www.latex-project.org/cgi-bin/ltxbugs2html.new?pr=tools/3512

* Low bit of dpc is read-only.

* Defer specifics of dpc writability to the priv spec.

* Revert to PDF from master

Move some text out of an explanation block. It's awkward to start a
Section with one, and also the text doesn't make sense without reading
the explanation.

Clarify this by explicitly saying the behavior only applies to
running/halted harts respectively.

* Clarify stoptime behavior.

More accurate state the behavior specified in Section 4.1, so people
don't have to read that in order to really understand this part.

See #766.

* Replace "snap forward" with clearer language

Co-authored-by: Paul Donahue <48959409+pdonahue-ventana@users.noreply.github.com>
Signed-off-by: Tim Newsome <tim@sifive.com>

* Multi-hart implementations will likely wire stoptime=0

Signed-off-by: Tim Newsome <tim@sifive.com>
Co-authored-by: Paul Donahue <48959409+pdonahue-ventana@users.noreply.github.com>

Previously the spec could be interpreted to mean that dmode is ignored
for trigger type 15. Fix this ambiguity and, for consistency, make it so
dmode is active for trigger type 15.

* abstractcs.relaxedpriv: Clarify the description

Changed the wording in the description of "abstractcs.relaxedpriv"
field in order to make the meaning of that field clear:

- full permissions --> full permission checks
- relaxed permissions --> relaxed permission checks

The original wording may have suggested the opposite meaning.

* Updated xml/dm_registers.xml per suggestion - added <value> tags

Co-authored-by: Tim Newsome <tim@sifive.com>
Signed-off-by: Jan Matyas <50193733+JanMatCodasip@users.noreply.github.com>

Signed-off-by: Jan Matyas <50193733+JanMatCodasip@users.noreply.github.com>
Co-authored-by: Tim Newsome <tim@sifive.com>

It's not clear, as reported in #760.

It doesn't matter what the values are after write/nop, so explicitly
state that.

Address feedback from architecture review