Add cross link back to the RISCV Working Group overview

Generate chisel

serial: tweak addresses

I didn't quite understand what was going on.

Add explicit type field to Abstract Command.

Finish up replacement of ibuf->progbuf

Remove last references to "Instruction Supply"

Also changed accesscs register to "progbufcs", since
it is specific to the program buffer control and status.

Clarify that the halt state of all harts is maintained through reset

This addresses the question from me on the mailing list and in today's
meeting. There were a few similar questions, so it seems worthwhile to
make things more explicit.

Use consistent 'Control and Status' naming for CS registers.

sm_diagram: Show using resumereq bit to resume.

The debug spec doesn't care what you do with them.