Marked as Ratified.

Signed-off-by: Nicolas Brunie <82109999+nibrunieAtSi5@users.noreply.github.com>

[Zvk Code Samples] Add vgmul test, document zvbc/zvkg tests, TESTED_VLENS parameter, GCC fixes (#340)

* [Zvk Code Samples] Add vgmul test, document zvbc/zvkg tests

- Document the existence of Makefile targets 'zvbc-test' and
  'run-zvbc'.
- Add a test ('zvkg-test', 'run-zvkg') that validates
  the Zvkg instruction 'vgmul.vv' by using 'vghsh.vv'
  as the reference implementation. vghsh is validated
  in aes-gcm-test, so it can be used to generate expected
  outputs to validate vgmul.

Signed-off-by: Eric Gouriou <ego@rivosinc.com>

* [Zvk Code Samples] Allow overriding tested VLEN values

As suggested by Nicolas Brunie.

Instead of repeating the list of VLEN values, introduce
the variable TESTED_VLENS which can be overridden from
the commandline.

Some tests do not have support for VLEN=64. Logic is added
to skip those invocations that otherwise end in failure.

Signed-off-by: Eric Gouriou <ego@rivosinc.com>

* [Zvk Code Samples] Fix GCC issues

- In aes-gcm-test.c, GCC gives up on -Wmisleading-indentation
  due to the size of the includes and emits a warning. Adding
  braces on the if/for statements cleans up the compilation.
- In zvknh.s, GAS errors out on // line comments that LLVM
  accepts. Correct them to use '#' instead.

Signed-off-by: Eric Gouriou <ego@rivosinc.com>

---------

Signed-off-by: Eric Gouriou <ego@rivosinc.com>

Date and revremark

Signed-off-by: Rafael Sene <rafael@riscv.org>

Corrected the spelling of Allen's name

Update date and revision

Signed-off-by: Rafael Sene <rafael@riscv.org>

Added more clarity to when the mask is not subject to DIEL.

* minor fixes (vbrev in zvkb list) + zvksed in DIEL

* typo in riscv-crypto-vector-zvkt.adoc

Signed-off-by: Nicolas Brunie <82109999+nibrunieAtSi5@users.noreply.github.com>

* Update vbrev.adoc

Signed-off-by: Nicolas Brunie <82109999+nibrunieAtSi5@users.noreply.github.com>

* Update riscv-crypto-vector-zvkb.adoc

Signed-off-by: Nicolas Brunie <82109999+nibrunieAtSi5@users.noreply.github.com>

---------

Signed-off-by: Nicolas Brunie <82109999+nibrunieAtSi5@users.noreply.github.com>

Removing Zvkb from the "Included in".
vbrev.v is a general purpose instruction and is not needed for our crypto instructions.

* fixing typo Zvkc -> Zvknc in vclmul*

* fixing extension list for vrev8

Cleaned up and updated "Included in at bottom of pages"
Added a new extension Zvkb for Vector Cryptography Bit-Manipulation
   This is a proper subset of Zvbb and only includes the instructions needed for cryptography
Updated Zvkt to say that DIEL doesn't apply to constants included in the instruction encoding such as immediate values  and the zero register.

As discovered by @shakakao and reported by @nibrunieAtSi5
(see https://github.com/riscv/riscv-crypto/issues/331), the
Zvbc-based GHASH logic incorrectly relies on vxor to leave
masked-off lanes undisturbed even though it sets the vector
state with a mask agnostic policy.

The fix is to use ", mu" to request masked-off elements to be
undisturbed.

I did check all proof-of-concept tests in an environment where
masked-off elements get overwritten when "ma" is in effect.
Prior to those fixes only the 'aes-gcm-test' fails, and all
pass with those fixes.

Fixes: https://github.com/riscv/riscv-crypto/issues/331



Signed-off-by: Eric Gouriou <ego@rivosinc.com>

Signed-off-by: Nicolas Brunie <82109999+nibrunieAtSi5@users.noreply.github.com>

Signed-off-by: Nicolas Brunie <82109999+nibrunieAtSi5@users.noreply.github.com>
`Zvkb` replaced with `Zvbb` and `Zvbc`

The document is now frozen and ready for public review.

Clarify that vwsll zero-extends the vs2 operand

This follows from the SAIL code and arguably from the instruction's
mnemonic, but make it explicit for readers' benefit.

Fix typo in riscv-crypto-vector-element-groups.adoc

Bumped date and rev

At the request of the Unprivileged Architecture Standing Committee,  we added NIST/ShangMi combined with carryless multiply as a lower cost and lower performance alternative to GCM/GMAC combinations.

fixing vctz vd description

Update vaese128.adoc

Honestly the smallest typo but I figure why not propose the change. vd is used in place of vs2 when describing the purpose of the register (storing plain text).

Signed-off-by: Xavier Esteve <xjesteve@gmail.com>

Signed-off-by: Nicolas Brunie <82109999+nibrunieAtSi5@users.noreply.github.com>

Fixed email address of editor

Zvk code samples  / Proof of Concept (v2)

Bumping the rev and date.

At the recommendation of the ARC, we have removed carryless multiply from the list of extensions included in Zvkn and Zvks.
We recommendation that Zvbc is implemented in RISC-V Vector designs as it enables implementation of CRC and elliptic curve cryptography.