The linker doesn't allocate memory space for sections that are only SEC_ALLOC
and SEC_THREAD_LOCAL.  See the IS_TBSS test in ld/ldlang.c.  So we need to
pretend that .tdata.dyn sections have contents to get the right result.  It
will be marked this way anyways if there is a .tdata section to merge with.

	bfd/
	PR 23825
	* elfnn-riscv.c (riscv_elf_create_dynamic_sections): Add SEC_LOAD,
	SEC_DATA, and SEC_HAS_CONTENTS to .tdata.dyn section.

This was noticed while trying to test the compiler -msave-restore support.
Putting non-pic code in a shared library gives a linker error, but doesn't
stop the build.

rohan:2030$ cat libtmp.c
extern int sub2 (int);
int sub (int i) { return sub2 (i + 10); }
rohan:2031$ cat libtmp2.c
extern int sub (int);
int sub2 (int i) { return sub (i + 10); }
rohan:2032$ riscv64-unknown-linux-gnu-gcc --shared -o libtmp.so libtmp.c
rohan:2033$ riscv64-unknown-linux-gnu-gcc --shared -o libtmp2.so libtmp2.c libtmp.so
/home/jimw/FOSS/install-riscv64/lib/gcc/riscv64-unknown-linux-gnu/8.3.0/../../../../riscv64-unknown-linux-gnu/bin/ld: /tmp/cctrsIBe.o(.text+0x18): unresolvable R_RISCV_CALL relocation against symbol `sub'
rohan:2034$ echo $?
0
rohan:2035$ ls -lt libtmp2.so
-rwxr-xr-x 1 jimw jimw 6912 Aug 30 14:32 libtmp2.so
rohan:2036$

The patch fixes this by forcing a linker error.  I now get this.

ohan:2059$ sh tmp.script
/home/jimw/FOSS/BINUTILS/X-riscv64-linux/ld/ld-new: libtmp2.o(.text+0x18): unresolvable R_RISCV_CALL relocation against symbol `sub'
/home/jimw/FOSS/BINUTILS/X-riscv64-linux/ld/ld-new: final link failed: bad value
rohan:2060$ echo $?
1
rohan:2061$ ls -lt libtmp2.so
ls: cannot access 'libtmp2.so': No such file or directory

	bfd/
	* elfnn-riscv.c (riscv_elf_relocate_section): For unresolvable reloc
	error, call bfd_set_error, set ret to FALSE, and goto out label.

This was broken when I changed how we compute the value for the gp register.
It used to be computed inside the sdata section.  Now it is computed at the
end which makes it an abs section symbol.  There is code that tries to use
the alignment of the section that the gp value is in, but this does not work
if it is in the abs section, as the abs section has alignment of 1 byte.
There are people using alternative linker scripts that still define it in the
sdata section, so the code is still useful.  Thus adding a check to disable
this when gp is in the abs section.

	bfd/
	* elfnn-riscv.c (_bfd_riscv_relax_lui): Add check to exclude abs
	section when setting max_alignment.  Update comment.
	(_bfd_riscv_relax_pc): Likewise.

This fixes a problem originally reported at
    https://github.com/riscv/riscv-binutils-gdb/issues/173

If you have code linked at address zero, you can have a lui instruction
loading a value 0x800 which gets relaxed to a c.lui which is valid (c.lui 0x1
followed by addi -0x800).  Relaxation can reduce the value below 0x800 at which
point the c.lui 0x0 is no longer valid.  We can fix this by converting the
c.lui to a c.li which can load 0.

	bfd/
	* elfnn-riscv.c (perform_relocation) <R_RISCV_RVC_LUI>: If
	RISCV_CONST_HIGH_PART (value) is zero, then convert c.lui instruction
	to c.li instruction, and use ENCODE_RVC_IMM to set value.

	ld/
	* testsuite/ld-riscv-elf/c-lui-2.d: New.
	* testsuite/ld-riscv-elf/c-lui-2.ld: New.
	* testsuite/ld-riscv-elf/c-lui-2.s: New.
	* testsuite/ld-riscv-elf/ld-riscv-elf.exp: Run the c-lui-2 test.

	bfd/ChangeLog
	Ilia Diachkov  <ilia.diachkov@optimitech.com>
	* elfnn-riscv.c (_bfd_riscv_relax_lui): Set lui relax safety area to
	two pages in relro presence.

	Mel Chen <mel.chen@sifive.com>
	gas/
	* testsuite/gas/riscv/alias-csr.s: Add testcase for CSR-access
	alias instructions.
	* testsuite/gas/riscv/no-aliases-csr.d: Run testcase alias-csr.s with
	-Mno-aliases.
	* testsuite/gas/riscv/alias-csr.d: Run testcase alias-csr.s.
	* testsuite/gas/riscv/priv-reg.d: Update.
	opcodes/
	* riscv-opc.c (riscv_opcodes): Set frsr, fssr, frcsr, fscsr, frrm,
	fsrm, fsrmi, frflags, fsflags, fsflagsi to alias instructions.
	* riscv-opc.c (riscv_opcodes): Adjust order of frsr, frcsr, fssr,
	fscsr.

	From Kito Cheng <kito.cheng@sifive.com>
	gas/ChangeLog
	* doc/c-riscv.texi (Instruction Formats): Add r4 type.
	* testsuite/gas/riscv/insn.d: Add testcase for r4 type.
	* testsuite/gas/riscv/insn.s: Ditto.
	* doc/c-riscv.texi (Instruction Formats): Add b and j type.
	* testsuite/gas/riscv/insn.d: Add test case for b and j type.
	* testsuite/gas/riscv/insn.s: Ditto.
	* testsuite/gas/riscv/insn.s: Correct instruction type for load
	and store.
	* testsuite/gas/riscv/insn.d: Using regular expression to match
	address.
	* doc/c-riscv.texi (Instruction Formats): Fix encoding table for SB
	type and fix typo.
	opcode/ChangeLog
	* riscv-opc.c (riscv_insn_types): Add r4 type.
	* riscv-opc.c (riscv_insn_types): Add b and j type.
	* opcodes/riscv-opc.c (riscv_insn_types): Remove incorrect
	format for sb type and correct s type.

Without the ELF header to set info->endian, it ends up as BFD_UNKNOWN_ENDIAN
which gets printed as big-endian.  But RISC-V instructions are always little
endian, so we can set endian_code correctly, and then set display_endian from
that.  This is similar to how the aarch64 support works, but without the
support for constant pools, as we don't have that on RISC-V.

	opcodes/
	PR binutils/24739
	* riscv-dis.c (riscv_disasemble_insn): Set info->endian_code.
	Set info->display_endian to info->endian_code.

	2019-06-24  Ilia Diachkov  <ilia.diachkov@optimitech.com>
	bfd/
	* elfnn-riscv.c (_bfd_riscv_relax_lui): Delete early exit when
	SEC_MERGE or SEC_CODE flags are set.
	(_bfd_riscv_relax_section): New local symtype.  Set sym_sec and
	symtype consistently.  Don't include sec_addr (sym_sec) in symval.
	Add check for SEC_INFO_TYPE_MERGE and call _bfd_merged_section_offset.
	Add sec_addr (sym_sec) after handling merge sections.

This fixes a bug reported on the riscv.org sw-dev mailing list.  This
rejects "lui x1,symbol", as a symbol should only be accepted here when
used inside %hi().  Without the fix, this gets assembled as "lui x1,0"
with no relocation which is clearly wrong.

	gas/
	* config/tc-riscv.c (riscv_ip) <'u'>: Move O_constant check inside if
	statement.  Delete O_symbol and O_constant check after if statement.
	* testsuite/gas/riscv/auipc-parsing.s: Test lui with missing %hi.
	* testsuite/gas/riscv/auipc-parsing.l: Update.

	bfd/
	* elfnn-riscv.c (PRSTATUS_SIZE) [ARCH_SIZE==32]: Change from 0 to 204.

This fixes a glib build failure reported in PR 24389.  Using ld -b binary
creates an object file with no elf header flags set which has the wrong ABI
info for riscv64-linux.  But the file also has no code sections, so I added
code borrowed from the arm port that only checks the ELF header ABI flags if
there is a code section.

	bfd/
	PR 24389
	* elfnn-riscv.c (_bfd_riscv_elf_merge_private_bfd_data): Move read of
	ELF header flags to after check for ELF object file.  Loop through
	sections looking for code sections, if none, then skip ABI checks.

	2019-03-30  Andrew Waterman  <andrew@sifive.com>
	bfd/
	* elfnn-riscv.c (_bfd_riscv_relax_call): Only check ARCH_SIZE for
	rd == X_RA case.

sym is only set for local symbols.  h is only set for global symbols.  Gas
won't let me create a global section symbol, but bfd appears to have some
support for that, and I can't rule out that other assemblers might do this.
So we need to support both, and verify sym and h are non-NULL before using.

	bfd/
	PR 24365
	* elfnn-riscv.c (riscv_elf_relocate_section): For STT_SECTION check,
	verify sym non-NULL before using.  Add identical check using h.

This lets us accept an instruction like
	beq a2,x0,.Label
and generate a compressed beqz.  This will allow some future simplications
to the gcc support, e.g. eliminating some duplicate patterns, and avoiding
adding new duplicate patterns, since currently we have to handle signed
and equality compares against zero specially.

Tested with rv{32,64}-{elf,linux} cross builds and make checks for binutils
and gcc.  There were no regressions.

	gas/
	* config/tc-riscv.c (validate_riscv_insn) <'C'>: Add 'z' support.
	(riscv_ip) <'C'>: Add 'z' support.
	opcodes/
	* riscv-opc.c (riscv_opcodes) <beq>: Use Cz to compress 3 operand form.
	<bne>: Likewise.

opcodes/ChangeLog:

2019-01-31  Andreas Krebbel  <krebbel@linux.ibm.com>

	Backport from mainline
	2019-01-31  Andreas Krebbel  <krebbel@linux.ibm.com>

	* s390-mkopc.c (main): Accept arch13 as cpu string.
	* s390-opc.c: Add new instruction formats and instruction opcode
	masks.
	* s390-opc.txt: Add new arch13 instructions.

include/ChangeLog:

2019-01-31  Andreas Krebbel  <krebbel@linux.ibm.com>

	Backport from mainline
	2019-01-31  Andreas Krebbel  <krebbel@linux.ibm.com>

	* opcode/s390.h (enum s390_opcode_cpu_val): Add
	S390_OPCODE_ARCH13.

gas/ChangeLog:

2019-01-31  Andreas Krebbel  <krebbel@linux.ibm.com>

	Backport from mainline
	2019-01-31  Andreas Krebbel  <krebbel@linux.ibm.com>

	* config/tc-s390.c (s390_parse_cpu): New entry for arch13.
	* doc/c-s390.texi: Document arch13 march option.
	* testsuite/gas/s390/s390.exp: Run the arch13 related tests.
	* testsuite/gas/s390/zarch-arch13.d: New test.
	* testsuite/gas/s390/zarch-arch13.s: New test.
	* testsuite/gas/s390/zarch-z13.d: Expect the renamed mnemonics
	also for z13.

gcc-9 flagged warnings at the places I'm patching here, all real bugs.

	* config/tc-alpha.c (md_apply_fix): Correct range checks for
	BFD_RELOC_ALPHA_NOP, BFD_RELOC_ALPHA_LDA, BFD_RELOC_ALPHA_BSR.
	* config/tc-arm.c (md_apply_fix): Use llabs rather than abs.
	* config/tc-csky.c (get_macro_reg_vals): Pass s to csky_show_error.

(cherry picked from commit 3ca4a8ec)

	* NEWS: Mention -t change.
	* ld.texi (--trace/-t): Expand documentation a little.

(cherry picked from commit 4f4690cd)

xtensa gas chokes on 8/16 bit data entries representing constant symbols
because it leaves BFD_RELOC_8/BFD_RELOC_16 fixups for which xtensa BFD
cannot emit relocations. Resolve fixups for constant symbols in
md_apply_fix.

gas/
2019-01-29  Max Filippov  <jcmvbkbc@gmail.com>

	* config/tc-xtensa.c (md_apply_fix): Mark fixups for constant
	symbols as done in md_apply_fix.
	* testsuite/gas/all/forward.d: Don't XFAIL for xtensa.

	* configure.ac (ac_checking): Set from bfd/development.sh
	development variable.
	* configure: Regenerate.

(cherry picked from commit e044973b)

	PR 24008
	* ldexp.h (lang_phase_type): Add lang_fixed_phase_enum.
	* ldexp.c (fold_name): Move expld.assign_name check later to
	avoid an extra lookup.
	(exp_fold_tree_1): When lang_fixed_phase_enum, don't change symbol
	values, and don't clear expld.assign_name.
	* ldlang.c (lang_map): Set expld.phase to lang_fixed_phase_enum.
	(print_assignment): Resolve entire assignment expression.
	Don't access symbol u.def unless symbol is defined.

The test is already skipped on PowerPC and Aarch64 because it's invalid.

	* testsuite/ld-ifunc/ifunc.exp: Skip pr23169 on SPARC.

	* elf32-arm.c (elf32_arm_final_link_relocate): Use 'llabs' instead
	of 'labs' (and fix GCC warning).

(cherry picked from commit e10620d3)

This patch is part of a series of patches to introduce a few changes to the
Armv8.5-A Memory Tagging Extension. This patch updates the st*g instructions
to use a previously reserved field for a new register operand. Thus the
new versions of the instructions are as follows:

- STG Xt, [<Xn|SP>, #<simm>]
- STG Xt, [<Xn|SP>, #<simm>]!
- STG Xt, [<Xn|SP>], #<simm>
- STZG Xt, [<Xn|SP>, #<simm>]
- STZG Xt, [<Xn|SP>, #<simm>]!
- STZG Xt, [<Xn|SP>], #<simm>
- ST2G Xt, [<Xn|SP>, #<simm>]
- ST2G Xt, [<Xn|SP>, #<simm>]!
- ST2G Xt, [<Xn|SP>], #<simm>
- STZ2G Xt, [<Xn|SP>, #<simm>]
- STZ2G Xt, [<Xn|SP>, #<simm>]!
- STZ2G Xt, [<Xn|SP>], #<simm>

Committed on behalf of Sudakshina Das.

*** gas/ChangeLog ***

	* config/tc-aarch64.c (warn_unpredictable_ldst): Exempt
	stg, st2g, stzg and stz2g from Xt == Xn with writeback warning.
	* testsuite/gas/aarch64/armv8_5-a-memtag.d: Change tests for
	stg, stzg, st2g and stz2g.
	* testsuite/gas/aarch64/armv8_5-a-memtag.s: Likewise.
	* testsuite/gas/aarch64/illegal-memtag.l: Likewise.
	* testsuite/gas/aarch64/illegal-memtag.s: Likewise.

*** opcodes/ChangeLog ***

	* aarch64-tbl.h (QL_LDST_AT): Update macro.
	(aarch64_opcode): Change encoding for stg, stzg
	st2g and st2zg.
	* aarch64-asm-2.c: Regenerated.
	* aarch64-dis-2.c: Regenerated.
	* aarch64-opc-2.c: Regenerated.

(cherry picked from commit 69105ce4)

This patch is part of a series of patches to introduce a few changes to the
Armv8.5-A Memory Tagging Extension. This patch adds the new STZGM instruction.

STGZM Xt, [<Xn|SP>]

Committed on behalf of Sudakshina Das.

*** gas/ChangeLog ***

	* testsuite/gas/aarch64/armv8_5-a-memtag.d: New tests for stzgm.
	* testsuite/gas/aarch64/armv8_5-a-memtag.s: Likewise.
	* testsuite/gas/aarch64/illegal-memtag.l: Likewise.
	* testsuite/gas/aarch64/illegal-memtag.s: Likewise.

*** opcodes/ChangeLog ***

	* aarch64-asm-2.c: Regenerated.
	* aarch64-dis-2.c: Likewise.
	* aarch64-opc-2.c: Likewise.
	* aarch64-tbl.h (aarch64_opcode): Add new stzgm.

(cherry picked from commit 20a4ca55)

This patch is part of a series of patches to introduce a few changes to the
Armv8.5-A Memory Tagging Extension. This patch removes the LDGV and STGV
instructions. These instructions needed special infrastructure to support
[base]! style for addressing mode. That is also removed now.

Committed on behalf of Sudakshina Das.

*** gas/ChangeLog ***

	* config/tc-aarch64.c (parse_address_main): Remove support for
	[base]! address expression.
	(parse_operands): Remove support for AARCH64_OPND_ADDR_SIMPLE_2.
	(warn_unpredictable_ldst): Remove support for ldstgv_indexed.
	* testsuite/gas/aarch64/armv8_5-a-memtag.d: Remove tests for ldgv
	and stgv.
	* testsuite/gas/aarch64/armv8_5-a-memtag.s: Likewise.
	* testsuite/gas/aarch64/illegal-memtag.l: Likewise.
	* testsuite/gas/aarch64/illegal-memtag.s: Likewise.

*** include/ChangeLog ***

	* opcode/aarch64.h (enum aarch64_opnd): Remove
	AARCH64_OPND_ADDR_SIMPLE_2.
	(enum aarch64_insn_class): Remove ldstgv_indexed.

*** opcodes/ChangeLog ***

	* aarch64-asm.c (aarch64_ins_addr_simple_2): Remove.
	* aarch64-asm.h (ins_addr_simple_2): Likeiwse.
	* aarch64-dis.c (aarch64_ext_addr_simple_2): Likewise.
	* aarch64-dis.h (ext_addr_simple_2): Likewise.
	* aarch64-opc.c (operand_general_constraint_met_p): Remove
	case for ldstgv_indexed.
	(aarch64_print_operand): Remove case for AARCH64_OPND_ADDR_SIMPLE_2.
	* aarch64-tbl.h (struct aarch64_opcode): Remove ldgv and stgv.
	(AARCH64_OPERANDS): Remove ADDR_SIMPLE_2.
	* aarch64-asm-2.c: Regenerated.
	* aarch64-dis-2.c: Regenerated.
	* aarch64-opc-2.c: Regenerated.

(cherry picked from commit 550fd7bf)