* RISC-V: enable have_nonsteppable_watchpoint by default

The RISC-V debug spec 0.13 recommends that write triggers fire before
the write is committed. If the target follows this behaviour, then
have_nonsteppable_watchpoint needs to be set to 1 so that GDB will step
over the watchpoint before checking if the value has changed.

This patch adds a setshow for have_nonsteppable_watchpoint which
defaults to 1 to match the recommended behaviour. If a target does not
follow this timing, then 'set riscv have_nonsteppable_watchpoint 0'
will need to be issued on the command line.

gdb/ChangeLog:

	* riscv-tdep.c (set_have_nonsteppable_watchpoint): add
	callback for 'set riscv have_nonsteppable_watchpoint'
	(riscv_gdbarch_init): initialise gdbarch setting for
	have_nonesteppable_watchpoint

* Add changes following comments on upstream patch

Adds a show method for 'show riscv have-nonsteppable-watchpoint'
plus additional comment and formatting fixes.

gdb/ChangeLog:

	* riscv-tdep.c (show_have_nonsteppable_watchpoint): Add
	callback for 'show riscv have-nonsteppable-watchpoint'.

* Bring mstatus up-to-date with latest privspec.

Requested by https://github.com/riscv/riscv-openocd/issues/249

* Use tabs where possible, for consistency.

Complete full reg list if some aren't readable

Previously `info all-registers` and `info registers all` would terminate
as soon as it got to a register that was not readable. Now the user gets
a message and the register list continues.

	ld/
	* emulparams/elf32lriscv-defs.sh (GENERATE_SHLIB_SCRIPT): Move inside
	case on $target, and don't set for riscv*-elf targets.
	(GENERATE_PIE_SCRIPT): Likewise.

Ignore errors when reading register to save them

Debug servers may not be able to determine exactly which registers exist
on a target, meaning in turn that gdb can't be sure. When gdb goes to
save these registers before a function call, failure to read one of them
should not be fatal.

This change ignores these failures. Registers that were not read, will
not be restored.

Unfortunately for each register that can't be read there will be a
message to the user. Getting rid of that message only for this use case
is not trivial, so I'm punting on it for now.

	ld/
	* testsuite/lib/ld-lib.exp (check_shared_lib_support): Return false
	for riscv*-*-elf.

Fix mingw builds on Windows.

	gas/
	* testsuite/gas/riscv/priv-reg.d, testsuite/gas/riscv/priv-reg.s: New.

	include/
	* opcode/riscv-opc.h (DECLARE_CSR): Add missing privileged registers.
	Sort to match privileged spec documentation order.
	(DECLARE_CSR_ALIAS): Add ubadaddr, and comments.

	gas/
	* config/tc-riscv.c (risc_ip) <o>: Add comment.
	* testsuite/gas/riscv/c-nonzero-imm.d,
	* testsuite/gas/riscv/c-nonzero-imm.l,
	* testsuite/gas/riscv/c-nonzero-imm.s,
	* testsuite/gas/riscv/c-nonzero-reg.d,
	* testsuite/gas/riscv/c-nonzero-reg.l,
	* testsuite/gas/riscv/c-nonzero-reg.s,
	* testsuite/gas/riscv/c-zero-imm-64.d,
	* testsuite/gas/riscv/c-zero-imm-64.s,
	* testsuite/gas/riscv/c-zero-imm.d, testsuite/gas/riscv/c-zero-imm.s,
	* testsuite/gas/riscv/c-zero-reg.d,
	* testsuite/gas/riscv/c-zero-reg.s: New.

	opcodes/
	* riscv-opc.c (match_c_add_with_hint, match_c_lui_with_hint): New.
	(riscv_opcodes) <li>: Delete "d,0" line.  Change Cj to Co.
	<andi, and, add, addiw, addw, c.addi>: Change Cj to Co.
	<add>: Add explanatory comment for 4-operand add instruction.
	<c.nop>: Add support for immediate operand.
	<c.mv, c.add>: Use match_c_add_with_hint instead of match_c_add.
	<c.lui>: Use match_c_lui_with_hint instead of match_c_lui.
	<c.li, c.slli>: Use match_opcode instead of match_rd_nonzero.

	PR 22599
	gas/
	* testsuite/gas/riscv/fsxxi.d, testsuite/gas/riscv/fsxxi.s: New.
	opcodes/
	* riscv-opc.c (riscv_opcodes) <fsrmi, fsflagsi>: New.

	PR 22465
	binutils/
	* objcopy.c (copy_section): New local extra.  If isection->lma not
	exactly divisible by interleave, then bias from.  Also adjust
	osection->lma if necessary.

	ld/
	* testsuite/ld-elf/interleave-0.d, testsuite/ld-elf/interleave-4.d,
	* testsuite/ld-elf/interleave.ld, testsuite/ld-elf/interleave.s: New.

	ld/
	* emulparams/elf32lriscv-defs.sh (SDATA_START_SYMBOLS): Remove HIDDEN.
	Don't define __global_pointer$ when CREATE_SHLIB.
	* testsuite/ld-riscv-elf/gp-hidden-64.rd,
	* testsuite/ld-riscv-elf/gp-hidden-lib.rd,
	* testsuite/ld-riscv-elf/gp-hidden-lib.s,
	* testsuite/ld-riscv-elf/gp-hidden-ver-64.rd,
	* testsuite/ld-riscv-elf/gp-hidden-ver.rd,
	* testsuite/ld-riscv-elf/gp-hidden-ver.s,
	* testsuite/ld-riscv-elf/gp-hidden-ver.ver,
	* testsuite/ld-riscv-elf/gp-hidden.rd,
	* testsuite/ld-riscv-elf/gp-hidden.s,
	* testsuite/ld-riscv-elf/gp-hidden.sd: Delete.
	* testsuite/ld-riscv-elf/gp-test-lib.sd,
	* testsuite/ld-riscv-elf/gp-test.s,
	* testsuite/ld-riscv-elf/gp-test.sd: New.
	* testsuite/ld-riscv-elf/ld-riscv-elf.exp: Rewrite gp tests.

	ld/
	* emulparams/elf32lriscv-defs.sh (SDATA_START_SYMBOLS): Mark
	__global_pointer$ as HIDDEN.
	* testsuite/ld-riscv-elf/gp-hidden-64.rd: New.
	* testsuite/ld-riscv-elf/gp-hidden-lib.rd: New.
	* testsuite/ld-riscv-elf/gp-hidden-lib.s: New.
	* testsuite/ld-riscv-elf/gp-hidden-ver-64.rd: New.
	* testsuite/ld-riscv-elf/gp-hidden-ver.rd: New.
	* testsuite/ld-riscv-elf/gp-hidden-ver.s: New.
	* testsuite/ld-riscv-elf/gp-hidder-ver.ver: New.
	* testsuite/ld-riscv-elf/gp-hidden.rd: New.
	* testsuite/ld-riscv-elf/gp-hidden.s: New.
	* testsuite/ld-riscv-elf/gp-hidden.sd: New.
	* testsuite/ld-riscv-elf/ld-riscv-elf.exp: Change riscv to riscv*.
	Run the new tests with run_ld_link_tests.

	gas/
	* doc/c-riscv.texi (RISC-V-Directives): Move @section immediately after
	@node.

	gas/
	* doc/as.texinfo (RISC-V): Alphabetize RISC-V entries.  Change
	RISC-V-Opts to RISC-V-Options.  Delete redundant space.  Add -fpic
	and related options to option list.
	* doc/c-riscv.texi: (RISC-V-Options): Renamed from RISC-V-Opts.
	(RISC-V Options): Renamed from Options.  Add missing period.
	(-fpic): Also mention -fPIC.
	(RISC-V Directives): New node.

	gas/
	* config/tc-riscv.c (riscv_frag_align_code): New local insn_alignment.
	Early return if bytes less than or equal to insn_alignment.
	* testsuite/gas/riscv/align-1.l: New.
	* testsuite/gas/riscv/align-1.s: New.
	* testsuite/gas/riscv/riscv.exp: Use run_dump_tests.  Use run_list_test
	for align-1.

Make native gdb builds work.

Don't show registers that don't exist

Also removed some out-of-date comments, and rewrote a comment.

By using the gdbarch functions we use the knowledge we got from the
target description. If there is no target description then we assumed
all the registers exist anyway.

This reverts commit 126050fc1f79749768ec95eb55abd62bd77058a1.

Per e-mail from Ulrich Weigand, this is not the right solution.

This came from an e-mail by Ulrich Weigand.

This ensures that a tdep's init function will be called with an info
struct that contains a target description if the `file` command is used
after connecting to a remote.

Now we update registers even if we have an arch already existing. Not
sure if that's right, but it at least works in the gdbserver.py tests.

Maybe more significant is that we look at register sizes to determine
the ABI. In theory this removes the need to set arch manually when
connecting without a file, fixing issue #54.

There are still a bunch of debug printfs that need to be removed before
merging.

GDB sim

Add support for servers that send an XML target description

Minor debug print/assert fixes.

Loads and stores with an explcit 0 offset were compressed, but loads and
stores with an implicit 0 offset were not compressed.  This patch fixes this
by handling a missing offset same as a zero offset.  This also adds tests
to check every case.  Verified on riscv32-elf and riscv64-elf, with check-gas,
check-binutils, and check-ld.  Committed.

	gas/
	* config/tc-riscv.c (riscv_handle_implicit_zero_offset): New.
	(riscv_ip): Cases 'k', 'l', 'm', 'n', 'M', 'N', add call to
	riscv_handle_implicit_zero_offset.  At label load_store, replace
	existing code with call to riscv_handle_implicit_zero_offset.
	* testsuite/gas/riscv/c-ld.d, testsuite/gas/riscv/c-ld.s: New.
	* testsuite/gas/riscv/c-lw.d, testsuite/gas/riscv/c-lw.s: New.
	* testsuite/gas/riscv/riscv.exp: Run new tests.

Add support for the new names of the RISC-V fmv.x.s and fmv.s.x instructions, vis: fmv.x.w and fmv.w.x.

	PR 22179
opcodes	* riscv-opc.c (riscv_opcodes): Add fmv.x.w and fmv.w.x as the new
	names for the fmv.x.s and fmv.s.x instructions respectively.

gas	* testsuite/gas/riscv/fmv.x.s: New file: Tests the support for the
	renamed fmv.x.s and fmv.s.x instructions.
	* testsuite/gas/riscv/fmv.x.d: New file: Test driver.