In the medany code model the compiler generates PCREL_HI20+PCREL_LO12
relocation pairs against local symbols because HI20+LO12 relocations
can't reach high addresses.  We relax HI20+LO12 pairs to GPREL
relocations when possible, which is an important optimization for
Dhrystone.  Without this commit we are unable to relax
PCREL_HI20+PCREL_LO12 pairs to GPREL when possible, causing a XX%
permormance hit on Dhrystone on Rocket.

Note that we'll now relax

  la gp, __global_pointer$

to

  mv gp, gp

which probably isn't what you want in your entry code.  Users who want
gp-relative symbols to continue to resolve should add ".option norelax"
accordingly.  Due to this, the assembler now pairs PCREL relocations
with RELAX relocations when they're expected to be relaxed.

We currently delete bytes by shifting an entire BFD backwards to
overwrite the bytes we no longer need.  The result is that relaxing a
BFD is quadratic time.

This patch adds an additional relocation that specifies a byte range
that will be deleted from the final object file, and adds a relaxation
pass (between the existing passes that delete bytes and the alignment
pass) that actually deletes the bytes.  Note that deletion is still
quadratic time, and nothing uses R_RISCV_DELETE yet.

R_RISCV_DELETE will never be emitted into ELF objects, so therefor isn't exposed
to the rest of binutils.

The symbol address in .eh_frame may be adjusted in
_bfd_elf_discard_section_eh_frame, and the content of .eh_frame will be
adjusted in _bfd_elf_write_section_eh_frame. Therefore, we cannot insert
a relocation whose addend symbol is in .eh_frame. Othrewise, the value
may be adjusted twice.

gas/ChangeLog

2017-05-11  Andrew Waterman  <andrew@sifive.com>

       * config/tc-riscv.c (riscv_ip): Changes as_warn to as_bad for improper
       shift amounts.

ChangeLog

2017-05-03  Kito Cheng  <kito.cheng@gmail.com>

        * riscv-dis.c (print_insn_args): Handle 'Co' operands.

ChangeLog:

* New RISC-V GDB port

e.g.

    1:  auipc ra, %pcrel_hi(symbol)
        jalr  ra, %pcrel_lo(1b)(ra)

The use of ra instead of t1 for address construction provides an
opportunity for a microarchitecture to elide the write of the
destination address, and instead read the target address as an
immediate spread across the fused auipc+jalr pair. The link
register ra in the jalr overwrites the target address temporary.

We've been telling people that the riscv32-* and riscv64-* toolchains
are exactly the same, but it turns out we were lying: the riscv32-* BFD
doesn't handle 64-bit objects.  This fixes that difference, so the ports
are actually the same.

bfd/ChangeLog

2017-05-01  Palmer Dabbelt  <palmer@dabbelt.com>

        * config.bfd (riscv32-*): Enable rv64.

We missed a "_gp" when changing the GP symbol.  To make sure that
doesn't happen again, we now use the same definition everywhere (thanks,
Nick).

include/ChangeLog:

2017-04-03  Palmer Dabbelt  <palmer@dabbelt.com>

        * elf/riscv.h (RISCV_GP_SYMBOL): New define.

bfd/ChangeLog:

2017-04-03  Palmer Dabbelt  <palmer@dabbelt.com>

        * elfnn-riscv.c (GP_NAME): Delete.
        (riscv_global_pointer_value): Change GP_NAME to RISCV_GP_SYMBOL.
        (_bfd_riscv_relax_lui): Likewise.

opcodes/ChangeLog:

2017-04-03  Palmer Dabbelt  <palmer@dabbelt.com>

        * riscv-dis.c (riscv_disassemble_insn): Change "_gp" to
        RISCV_GP_SYMBOL.

Complement commit e17b0c35 ("MIPS/BFD: Respect the ELF gABI dynamic
symbol table sort requirement") and correct an inconsistency in dynamic
symbol accounting data causing an assertion failure in the MIPS backend:

ld: BFD (GNU Binutils) 2.28.51.20170330 assertion fail
../../binutils-gdb/bfd/elfxx-mips.c:3860

in the course of making a GOT entry in a static binary to satisfy a GOT
relocation present in input, due to the local dynamic symbol count not
having been established.

To do so let backends request `_bfd_elf_link_renumber_dynsyms' to be
always called, rather than where a dynamic binary is linked only, and
then make this request in the MIPS backend.

	bfd/
	PR ld/21334
	* elf-bfd.h (elf_backend_data): Add `always_renumber_dynsyms'
	member.
	* elfxx-target.h [!elf_backend_always_renumber_dynsyms]
	(elf_backend_always_renumber_dynsyms): Define.
	(elfNN_bed): Initialize `always_renumber_dynsyms' member.
	* elfxx-mips.h (elf_backend_always_renumber_dynsyms): Define.
	* elflink.c (bfd_elf_size_dynsym_hash_dynstr): Also call
	`_bfd_elf_link_renumber_dynsyms' if the backend has requested
	it.
	(elf_gc_sweep): Likewise.

(backported from commit 23ec1e32)

Consistently call `_bfd_elf_link_renumber_dynsyms' only if linking a
dynamic binary, complementing code in `bfd_elf_size_dynsym_hash_dynstr'
and commit ccabcbe5 ("New attempt at fixing MIPS --gc-sections et
al."), <https://sourceware.org/ml/binutils/2005-08/msg00258.html>.

	bfd/
	* elflink.c (elf_gc_sweep): Only call
	`_bfd_elf_link_renumber_dynsyms' if dynamic sections have been
	created.

(backported from commit c46cec3a)

commit a27e4371
Author: Roland McGrath <roland@gnu.org>
Date:   Thu Jul 28 22:35:15 2011 +0000

    BFD vector for elf32-i386-nacl:

changed ELF_MAXPAGESIZE to 0x10000 for VxWorks.  This patch fixes it
and updated testsuite/ld-i386/vxworks2.sd to add space for program
headers.

bfd/

	PR ld/21425
	* elf32-i386.c (ELF_MAXPAGESIZE): Set to 0x1000 for VxWorks.

ld/

	PR ld/20815
	* testsuite/ld-i386/vxworks2.sd: Add space for program headers.

(cherry picked from commit 1587442d)

Backport (cherry-pick) from master.

	* elf32-arm.c (arm_type_of_stub): Supply missing args to "long
	branch veneers" error.  Fix double space and format message.
	* elf32-avr.c (avr_add_stub): Do not pass NULL as %B arg.
	* elf64-ppc.c (tocsave_find): Supply missing %B arg.