If the environment variables aren't set, then use the same defaults as
previously.

My current set of tools use riscv64-elf-gcc and riscv64-elf-gdb, and
this makes it trivial to use them.

- Replace general "Exception" with "GdbServerError" in gdbserver.py for when no
samples are collected
- Replace general "Exception" with "TargetsException" in targets.py for XLEN
mismatch
- Introduce "TestLibError" exception in testlib.py and replace general
exceptions in various locations
- Update pylint.rc to remove overgeneral-exceptions warning

New pylint, so make everything clean again.

Update OpenOCD cfg files to new syntax

We were using a variety of deprecated commands.

The driving force behind this was the new way to use `expr{}` as the old
way no longer works with mainline OpenOCD.

Include Zicntr in Spike ISA string

Add more tests for amo[max/maxu/min/minu]_w

Spike no longer enables Zicntr by default, so turn it on explicitly.

cc @jerryz123

Fix intermittent IcountTest failure on multi hart.

Don't build with -DMULTICORE because this is not a test that really does
multicore. It's one where we just want to park the other harts.

debug: fix pylint error W0621 redefined-outer-name

Add test for icount triggers.

Fix EtriggerTest on multi-hart targets.

The trap handler for norvc systems has an incorrect jump offset

Signed-off-by: Yujia Qiao <code@rapiz.me>

Related to issue https://github.com/riscv-software-src/riscv-tests/issues/453


It seems to be the only modification needed there.

It may break backward compatibility with (very?) old compilers.

Signed-off-by: Pascal Cotret <pascal.cotret@gmail.com>

env has been updated with trap and page fault filtering mechanism.
Such filtering allows tests to be written in such a way so that
exceptions/traps can be filtered by test case author and negative tests
can be written.

Signed-off-by: Deepak Gupta <debug@rivosinc.com>

Need to set the etrigger on the hart we're running the test against.

...because the ma_data test requires this feature.

Don't merge until https://github.com/riscv-software-src/riscv-isa-sim/pull/1206 is merged.

debug: Add Itrigger test.