Only works against spike, where I've implemented some custom debug
registers to test against.

Now that OpenOCD can tell gdb exactly which watchpoint was hit, this
test exposes another problem:
https://github.com/riscv/riscv-openocd/issues/295

For now neuter the test so the testsuite can still be useful.

@timsifive we are debugging intermittent failures.

This allows me to see the final valgrind output on OpenOCD, so I can
watch for memory leaks when using --server_cmd "valgrind
--leak-check=full openocd".

Add debug test, which checks that openocd correctly switch active thread on any hart halt.

It's failing (intermittently?). See eg.
https://travis-ci.org/riscv/riscv-tools/builds/418928412?utm_source=github_status&utm_medium=notification

The mstatus reading overwrites the expected user mode cause value.

This reverts commit 31a91823.

These changes should be made to the test environment, not the tests
themselves.

* making mtvec_handler global

* Adding the pmp configuration inst

The PMP config instructions are added as the test jumps to user mode

* Adding pmp config inst

Adding pmp config instructions as the test jumps to user mode

* changing to PMP macros

* changing to PMP Macros

* moving the #endif after pmp initialization

* Removing the unwanted label

https://github.com/riscv/riscv-isa-manual/commit/03a5e722fc0fe7b94dd0a49f550ff7b41a63f612

Newer gdb requires more debug info in order to "watch data" in this
test. I'm not sure how to make that debug info happen, so instead we
tell it the address to use.

Fix MulticoreRunHaltStepiTest

The test actually wasn't checking interrupt counts at all. Fixing it
required some other changes:
Make sure all harts get to run
Add some retries, since on a loaded machine against spike both harts
might not get to run, even if you give spike a generous amount of time
to do so.

Mark more Debug tests as "Single Hart"

* [rv64ua/lrsc] Initialize memory read out.

Even though the load contents are discarded, this un-initialized memory value
can lead to a divergence for co-simulation between two different RISC-V designs.

* [rv64ua/lrsc] Use .skip instead of .align.

debug: need to clear satp before changing priv

ISA Manual does not require this register to be reset, and attempting to execute code with VM on when VM hasn't been set up is going to just lead to sadness.

Delete E300Sim.py

debug: add missing align directive on trap_entry

This file is wrong (the .cfg file isn't right) and not used by anything.

Compute gdb command timeout based on ops estimate

The caller of gdb.command() should estimate how much work gdb needs to
do, and testlib then scales this up proportional to the general gdb
timeout we configured. This hopefully allows us to configure a tighter
timeout, so we don't have to have a multi-hour timeout just for
something that takes long like `load` on a really slow simulator.

Hopefully this addresses #122.