Test that we work correctly when the hart we're debugging ceases to
respond during stepi.

Add wait parameter to Gdb.stepi(), in case stepi isn't expected to complete.
Parse "could not read registers" error from gdb

Confirm basic debug still works when other harts have been parked using
a `cease` instruction. Check that the unavailable harts are inaccessible
from gdb.

Add Gdb.expect()
Parse "unknown thread" error from gdb.

Also make the semi-hosting test program return 10. That's more fragile
than returning 0, so makes for a better test.

It is allowed that M-mode only implementation could skip cycle/instret
if the Zicntr is not included.

Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>

Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>

This gives you less noise in the log, and more chance of figuring out
what code was actually executed.

`flush regs` is being deprecated.

`cease` is not a standard RISC-V extension, but is (was?) implemented in
Rocket, and also exists in some SiFive cores. It's useful to test
OpenOCD behavior when a hart becomes unavailable.

See also https://github.com/chipsalliance/rocket-chip/issues/1868

Also change the test itself to require less RAM than it did previously.
(It had required more than 32KB.)

It would fail intermittently. We can't guarantee all harts resume
simultaneously. When we let multiple harts run to a breakpoint at the
end of the same loop, one is likely to get there first, and the second
won't make it.

To avoid this problem, run for a short amount of time instead of to a
breakpoint.

Before it might fail incorrectly, because main was close to trap_entry.

* Specify trigger type=2 in trigger.S

Previous tests implicitly assume triggers only support type=2. However,
a trigger may support multiple types, i.e., type=15. This commit
explicitly specifies type=2 in trigger.S to support type 15.

* Update debug/programs/trigger.S

Co-authored-by: Tim Newsome <tim@sifive.com>
Signed-off-by: YenHaoChen <39526191+YenHaoChen@users.noreply.github.com>

Signed-off-by: YenHaoChen <39526191+YenHaoChen@users.noreply.github.com>
Co-authored-by: Tim Newsome <tim@sifive.com>

Between October 13 and October 19, something happened that makes the
multi-spike tests 4 times slower. Rolling back spike, OpenOCD, or
riscv-tests doesn't affect this. Presumably it's due to a kernel or
python change in my Ubuntu system.

I don't have time to look at this right now, so just increase the timeouts. :-(

If I had to guess, there could be a bug in rbb_daisychain.py that wastes
a lot of time.

https://github.com/riscv-software-src/riscv-isa-sim/pull/889 put a UART
at the address we were using in our 32-bit debug tests.

Fix long line to make pylint happy.

Get coverage of progbuf FPR accesses.

Using the new spike support merged in
https://github.com/riscv-software-src/riscv-isa-sim/pull/1109

debug: Add --debug_server arg to open gdb on OpenOCD

Not as useful as I'd like because we don't connect until after examine()
has completed, and the test is likely to time out while debugging. But
good to have, and maybe I'll expand on it one day.

update gdbserver.py; tolerance value of MemorySampleTest()

The control sequences (^[[?2004h and ^[[?2004l) occur after the
gdb.command, which results in Exception fault. This commit removes the
control sequences and strips out the blank lines (^M).

These can change at any time and that is OK.

I don't have time to fix the bug right now, and nobody has run into the
bug yet in any case.

Turn semihosting_fileio on for every hart. This test still fails if it
ends up running on hart 1 instead of 0, but at least it's closer to
passing. Feels like the remaining problem is in OpenOCD.

* Another pylint upgrade.

Lots of format string changes, which are more readable.

More files to come...

* Satisfy pylint for two more files.

The source of benchmarks' Makefile does not use fragments anymore. This commit removes the mention of them from the readme.

Signed-off-by: Mehmet Oguz Derin <mehmetoguzderin@mehmetoguzderin.com>

Assume that misaligned loads work correctly.

Passes `make -C isa run` against spike (both with and without misaligned
support).

Test misaligned stores

In the original test, confirm that stdout data ends up in the OpenOCD
log.
In the new test, with `arm semihosting_fileio` enabled, confirm that
stdout data ends up in gdb's CLI.

This test requires https://github.com/riscv/riscv-openocd/pull/699.

Cover lh, lw, and ld (only on rv64).