Merge branch 'lsu_allow_spec_load_exec' of github.com:riscv-software-src/riscv-perf-model into lsu_allow_spec_load_exec

Does not work yet. DO NOT MERGE

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Co-authored-by: Knute Lingaard <Knute.Lingaard@sifive.com>

Removed some dead code as well.

Added `void onStartingTeardown_() override {}` to the
LSU in this PR as an example. This method is called every time just
before the unit is destroyed -- either during an exception or a clean teardown.

Added new pipeline target: `f2i`. Fixed the JSONs to reflect the
intended source/dest direction.

Clang-format config based on the style guide in #87

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Signed-off-by: Suraj Shirvankar <surajshirvankar@gmail.com>

Signed-off-by: Knute Lingaard <knute.lingaard@sifive.com>

I kept the logic the same as it was earlier.
One of the design considerations was to use the BIU to communicate with
the cache and MMU.However it was later decided to keep the communication
simple until we design a more robust MMU design.

Same as #77 but the branch is in this repo instead of the fork

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Co-authored-by: vineethkm <vineethkm.01@gmail.com>
Co-authored-by: Knute Lingaard <Knute.Lingaard@sifive.com>

The goal of the PR is to improve build times.
Currently the build steps take around > ~15 mins and most of the time is
spent building sparta and the other dependencies.
This should bring it down to roughly ~6 mins.

CCache is used to cache build files, the cache for each branch is unique
to prevent cache invalidation issues between different branches.

Conda dependencies are also cached although the time to build is not
affected as much roughly ~1 mins but would be higher if the network is
slow.Conda spends a lot of time checking the dependencies.

Cached action run
https://github.com/h0lyalg0rithm/riscv-perf-model/actions/runs/5987171626

Adds separate tracking address/data operands for stores
(https://github.com/riscv-software-src/riscv-perf-model/issues/69).
Fixes isStore bug
(https://github.com/riscv-software-src/riscv-perf-model/issues/78

).
Fixes assertion bug in LSU.

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Signed-off-by: Aaron Chan <achn357@gmail.com>
Co-authored-by: Knute Lingaard <knute.lingaard@sifive.com>

This patchset adds documentation for generating coremark trace from
scratch.

Adding space after the message, as instruction details follow

Signed-off-by: avinash mehta <avinashmehtadelhi@gmail.com>

Addressing bug found in
https://github.com/riscv-software-src/riscv-perf-model/discussions/72