Signed-off-by: Knute <56927209+klingaard@users.noreply.github.com>

Added restrictions on supported programming languages

Signed-off-by: Knute <56927209+klingaard@users.noreply.github.com>

-> L2Cache can accept multiple requests from DCache and IL1.
-> Cache functional model used is SimpleDL1.
-> Configurable cache hit latency. 
-> Misses are forwarded to BIU and kept are tracked in the local buffer.
-> Miss to the pending cacheline is not sent out to BIU.
-> Backpressure handling for BIU credits.
-> make regress clean.

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Signed-off-by: Kunal-Buch <145377279+Kunal-Buch@users.noreply.github.com>
Co-authored-by: Knute <56927209+klingaard@users.noreply.github.com>

Fixed a couple of things:
1. Issue 126: bad character in ALF file generated from missing raw
string identifier for python: r"\1"
2. Added dependency in Makefile on the gen_alf.py script
3. Added error message when the MAP ALF generator cannot be found

Fix renaming to skip renaming of x0 outlined in
https://github.com/riscv-software-src/riscv-perf-model/issues/118

.

Changes:
- `renameInstructions_()` now checks if a source is x0, if it is and is
a data operand for a LSU operation, we still create a data register for
it, as we need to check in LSU for x0 before issuing instruction
- Added a boolean `x0` field to `Reg` struct in `RenameData` that tracks
if a data register is an `x0` instruction. This helps on reclamation of
rename credits in `getAckFromROB_()` to make sure we don't decrement for
an x0 data register
- Updated logic to handle for destination reclamation in
`getAckFromROB_()` to ensure when we reclaim credits/freelist
registers/references, we don't process them for x0 destinations
- Fixed initial allocation of freelist registers for `RF_INTEGER` to
only map registers for x1 - x31, before we were mapping from x0 - x31,
so we should technically see a performance improvement as we gained 1
extra freelist register from not renaming x0

---------

Signed-off-by: Aaron Chan <achn357@gmail.com>
Co-authored-by: Knute <56927209+klingaard@users.noreply.github.com>

Removed the old perl generator; uses the new python generator in Sparta.

These changes make a few assumptions: 
1. The user is using a newer version of sparta map_v2
2. The path to the clone of map is next to the clone of olympia

improve performance when stf tracing is enabled, issue #55 
 
retain n_cycles=10000 until the stf trace opc is detected. 
Once the stop opc is detected restore n_cycles=10000

result is better interactivity under linux, improving overall
performance and usability when not actively generating a trace.

This is a re-implementation of previous draft PR.

trace opc trigger detection is done in dromajo_template.
trace record creation and handling is done in dromajo_stf.cpp
headers gathered into dromajo_stf.h

---------

Co-authored-by: jeff <jeffnye-gh@github.com>

Change name of the SimpleDL1 class to a more generic name "SimpleCache3"

Fixing https://github.com/riscv-software-src/riscv-perf-model/issues/116

First cut of applied Clang format and new build rules for it.  We will slowly move
each and every file over to the new formats.

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Co-authored-by: Knute Lingaard <sparcians1@gmail.com>

Does not work yet. DO NOT MERGE

---------

Co-authored-by: Knute Lingaard <Knute.Lingaard@sifive.com>

Removed some dead code as well.

Added `void onStartingTeardown_() override {}` to the
LSU in this PR as an example. This method is called every time just
before the unit is destroyed -- either during an exception or a clean teardown.

Added new pipeline target: `f2i`. Fixed the JSONs to reflect the
intended source/dest direction.

Clang-format config based on the style guide in #87

---------

Signed-off-by: Suraj Shirvankar <surajshirvankar@gmail.com>

Signed-off-by: Knute Lingaard <knute.lingaard@sifive.com>

I kept the logic the same as it was earlier.
One of the design considerations was to use the BIU to communicate with
the cache and MMU.However it was later decided to keep the communication
simple until we design a more robust MMU design.

Same as #77 but the branch is in this repo instead of the fork

---------

Co-authored-by: vineethkm <vineethkm.01@gmail.com>
Co-authored-by: Knute Lingaard <Knute.Lingaard@sifive.com>

The goal of the PR is to improve build times.
Currently the build steps take around > ~15 mins and most of the time is
spent building sparta and the other dependencies.
This should bring it down to roughly ~6 mins.

CCache is used to cache build files, the cache for each branch is unique
to prevent cache invalidation issues between different branches.

Conda dependencies are also cached although the time to build is not
affected as much roughly ~1 mins but would be higher if the network is
slow.Conda spends a lot of time checking the dependencies.

Cached action run
https://github.com/h0lyalg0rithm/riscv-perf-model/actions/runs/5987171626

Adds separate tracking address/data operands for stores
(https://github.com/riscv-software-src/riscv-perf-model/issues/69).
Fixes isStore bug
(https://github.com/riscv-software-src/riscv-perf-model/issues/78

).
Fixes assertion bug in LSU.

---------

Signed-off-by: Aaron Chan <achn357@gmail.com>
Co-authored-by: Knute Lingaard <knute.lingaard@sifive.com>

This patchset adds documentation for generating coremark trace from
scratch.

Adding space after the message, as instruction details follow

Signed-off-by: avinash mehta <avinashmehtadelhi@gmail.com>

Addressing bug found in
https://github.com/riscv-software-src/riscv-perf-model/discussions/72

closes #64