Does not work yet. DO NOT MERGE

---------

Co-authored-by: Knute Lingaard <Knute.Lingaard@sifive.com>

Removed some dead code as well.

Added `void onStartingTeardown_() override {}` to the
LSU in this PR as an example. This method is called every time just
before the unit is destroyed -- either during an exception or a clean teardown.

Added new pipeline target: `f2i`. Fixed the JSONs to reflect the
intended source/dest direction.

Clang-format config based on the style guide in #87

---------

Signed-off-by: Suraj Shirvankar <surajshirvankar@gmail.com>

Signed-off-by: Knute Lingaard <knute.lingaard@sifive.com>

I kept the logic the same as it was earlier.
One of the design considerations was to use the BIU to communicate with
the cache and MMU.However it was later decided to keep the communication
simple until we design a more robust MMU design.

Same as #77 but the branch is in this repo instead of the fork

---------

Co-authored-by: vineethkm <vineethkm.01@gmail.com>
Co-authored-by: Knute Lingaard <Knute.Lingaard@sifive.com>

The goal of the PR is to improve build times.
Currently the build steps take around > ~15 mins and most of the time is
spent building sparta and the other dependencies.
This should bring it down to roughly ~6 mins.

CCache is used to cache build files, the cache for each branch is unique
to prevent cache invalidation issues between different branches.

Conda dependencies are also cached although the time to build is not
affected as much roughly ~1 mins but would be higher if the network is
slow.Conda spends a lot of time checking the dependencies.

Cached action run
https://github.com/h0lyalg0rithm/riscv-perf-model/actions/runs/5987171626

Adds separate tracking address/data operands for stores
(https://github.com/riscv-software-src/riscv-perf-model/issues/69).
Fixes isStore bug
(https://github.com/riscv-software-src/riscv-perf-model/issues/78

).
Fixes assertion bug in LSU.

---------

Signed-off-by: Aaron Chan <achn357@gmail.com>
Co-authored-by: Knute Lingaard <knute.lingaard@sifive.com>

This patchset adds documentation for generating coremark trace from
scratch.

Adding space after the message, as instruction details follow

Signed-off-by: avinash mehta <avinashmehtadelhi@gmail.com>

Addressing bug found in
https://github.com/riscv-software-src/riscv-perf-model/discussions/72

closes #64

Signed-off-by: Knute Lingaard <knute.lingaard@sifive.com>

Updated README with corrected build instructions.

Signed-off-by: Knute Lingaard <knute.lingaard@sifive.com>

Couple more things:
- Improved the performance of the simulator by reducing retire events
- Added param support to enable/disable skipping of non-user mode
instructions in an STF
- Added more debug messages
- Added Rename stall conditions/counters
- Fixed instruction status; was not being updated

Changing ExecutePipe.cpp code to set scoreboard based on destination
register, not the pipe register.
Added associated test for checking correct register file's rename
registers are used.

Summary of Changes:
LSU.cpp -> Operand dependency checking based on source bits in
scoreboard, callbacks
ExecutePipe.cpp -> Operand dependency checking based on source bits in
scoreboard, callbacks
Rename_test.cpp -> Added testing for both LSU and ExecutePipe with RAW
instruction jsons, imported OlympiaSim for full simulation run to access
data

Final portion of operand dependency checking implemented in this PR for
LSU and ExecutePipe.

---------

Signed-off-by: Aaron Chan <achn357@gmail.com>
Co-authored-by: Knute Lingaard <knute.lingaard@sifive.com>

Signed-off-by: Knute <56927209+klingaard@users.noreply.github.com>

Implementation of Task 1 for full Rename support:

Task 1: Add a arch map -> PRF map to Rename. 

This includes adding a physical register freelist (parameterized to the number). 
When an instruction enters rename, its source arch registers are mapped to the current
physical register for that arch value. Then its destination registers are renamed — 
a new PRF is pulled from the freelist, given to the instruction (via the scoreboard mask) 
and the rename map updated.

---------

Signed-off-by: Aaron Chan <achn357@gmail.com>
Co-authored-by: Aaron Chan <aaronchan@client-10-229-46-41.tamulink.tamu.edu>
Co-authored-by: Aaron Chan <aaronchan@Aarons-MacBook-Air-2.local>
Co-authored-by: Knute Lingaard <knute.lingaard@sifive.com>
Co-authored-by: Aaron Chan <aaronchan@Aarons-Air-2.attlocal.net>
Co-authored-by: Aaron Chan <aaronchan@client-10-228-106-204.tamulink.tamu.edu>

Signed-off-by: Suraj Shirvankar <surajshirvankar@gmail.com>

Signed-off-by: Suraj Shirvankar <surajshirvankar@gmail.com>

This fixes #35 and tracks the changes in Sparta
[PR397(https://github.com/sparcians/map/pull/397

), which are merges into Sparta main already. 

---------

Signed-off-by: Peter Debacker <peter-d@users.noreply.github.com>
Signed-off-by: Knute Lingaard <knute.lingaard@sifive.com>
Co-authored-by: Peter Debacker <pdback@imec.be>
Co-authored-by: Knute Lingaard <Knute.Lingaard@sifive.com>
Co-authored-by: Knute Lingaard <klingaard@gmail.com>

Small to change to  use all the CPU cores for the build.

Signed-off-by: Suraj Shirvankar <surajshirvankar@gmail.com>

Added directions to checkout map_v1.1.0

Signed-off-by: Knute Lingaard <knute.lingaard@sifive.com>

the path of WeightedContextCounter has been changed to
sparta/statistics, so fix it in this PR

First commit of using GitHub actions

Signed-off-by: Knute Lingaard <knute.lingaard@sifive.com>

---------

Signed-off-by: Knute Lingaard <knute.lingaard@sifive.com>
Co-authored-by: bdutro <brett.dutro@gmail.com>

Added specification for conda environment which can be used to build
olympia, stf lib/tools

- unmodified patch for dromajo, when applied, did not compile for
      me. Added a missing header file.

Added link to instructions to install required STF library packages

Signed-off-by: Knute Lingaard <knute.lingaard@sifive.com>

Signed-off-by: Knute <56927209+klingaard@users.noreply.github.com>

Signed-off-by: Knute Lingaard <knute.lingaard@sifive.com>

Adding a cast to get past the conversion error encountered during build.

Added a few additional LSU statistics. 

Output from running dhrystone trace:

```
        top.cpu.core0.lsu
            lsu_insts_dispatched                              = 5850001
            stores_retired                                    = 5850001
            lsu_insts_issued                                  = 11700073
            lsu_insts_completed                               = 5849999
            lsu_flushes                                       = 0
            tlb_hits                                          = 5850001
            tlb_misses                                        = 16
            dl1_cache_hits                                    = 5850000
            dl1_cache_misses                                  = 55
            biu_reqs                                          = 19

          top.cpu.core0.lsu.tlb
              tlb_hits                                        = 5850001
```

I will further look into the stats to make sure that they make sense.
But the added stats can now be used for the purpose of the demo.

The next step is adding rename function to let instructions fly via
Scoreboard 🙂