Cleanup on coding style (changed variables to match existing variables)

Removed extra whitespace

Bigger change:

- Removed the second stages for cache/mmu.

  These stages are not necessary.  Allow the machine to move instructions
  from MMU -> Cache and then check in the cache stage if the MMU hit
  was successful or not.  Do the same thing with Cache -> Complete.
  This allows a user to increase the MMU/Cache stages and not have
  to add new stages

- Fixed a bug where store instructions were actually not being marked
  complete at the correct time.

Overall perf difference from the original implementation and this new
one: none
Overall simulation performance different: slight increase (fewer ports,
fewer events).