Fixes the other half of #971.

Compared the start of this set of changes, it now takes 11% longer to
run the towers benchmark (with 22 discs).

Easier to read, maintaing, compiler errors, etc.

With this change, #971 is resolved for loads.

I haven't tested unaligned accesses, nor different endianness.

Easier to edit, better error messages from compiler, etc.

Slightly more readable than sizeof(type##_t) everywhere.

Only in slow path right now.

In preparation for checking accesses before they happen, when we only
know the address and not the data.

Include recently added headers in riscv/riscv.mk.in

Simplify decode_insn and insn_desc_t

Iterate over the instruction chains in reverse order, prioritizing
the last call to `disassembler_t::add_insn`.

To preserve behavior for the standard instructions, reverse the order
in which we add instructions in the `disassembler_t` constructor.

Supersedes #995.

We do not condition them on Zicbop/Zihintpause because,
definitionally, all implementations provide them.

Fixes bug introduced in 5b7cdbe1

The field is rendered unnecessary by 11f5942b.

Undoes some changes from 750f008e.

These add to the length of the instruction list without providing
an apparent benefit.

Fix for issue #990, implements the PBMTE bit in the henvcfg /menvcfg reisters

See #990.

Fix issue #990.

Also make PBMTE set on reset for backward compatibility.

Since before Spike proceeded as if these bits were set if the extension was enabled.

To do so implemented henvcfg_csr_t.

henvcfg.PBMTE will be read only 0 if menvcfg.PBMTE = 0.

rvv: fix the checking eew and elen for index load

eew of index register can't be larger than elen

ex:
   elen = 32,  vloxei64.v is illegal

Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>

Factor out P and V extension macros into their own headers

No functional change.

No functional change.

Implement Smepmp extension