Commits · private-l1-caches · github.com / riscv-software-src / riscv-isa-sim

Jun 08, 2020

Make L1 cache models private caches · 62412397

Andrew Waterman authored Jun 07, 2020

Previously, the cache simulator was basically modeling a multithreaded
core, rather than a homogeneous multicore, which is probably more useful.

62412397

May 30, 2020
- Merge pull request #475 from chihminchao/rvv-0.9 · 7246912c
  Andrew Waterman authored May 29, 2020
```
Rvv 0.9
```
  7246912c
May 29, 2020
- doc: update readme for vector 0.9 · 2469a571
  Chih-Min Chao authored May 28, 2020
```
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
```
  2469a571
- rvv: use zvqmac to enable vector qmac · 5ea3ef76
  Chih-Min Chao authored May 28, 2020
```
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
```
  5ea3ef76
- rvv: apply new overlapping and align macro · 09adc65e
  Chih-Min Chao authored May 27, 2020
```
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
```
  09adc65e
- rvv: add e8 type for narrow/widen conversion · 1bf9d025
  Chih-Min Chao authored May 27, 2020
```
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
```
  1bf9d025
- rvv: add new explicit eew load/store instructions · 36ebbb06
  Chih-Min Chao authored May 27, 2020
```
  1. unit
  2. stride
  3. index
  4. fault-first

Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
```
  36ebbb06
- rvv: add amo instructions · 3035256f
  Chih-Min Chao authored May 27, 2020
```
use --isa=rv64gcv_zvamo to enable it

Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
```
  3035256f
- rvv: add new singed/unsiged extension instructions · f5983b39
  Chih-Min Chao authored May 27, 2020
```
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
```
  f5983b39
- rvv: extenc VU structure to support 0.9 new fields · fb84a685
  Chih-Min Chao authored May 27, 2020
```
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
```
  fb84a685
- rvv: wrap align and overlap checking macro · d4f881d0
  Chih-Min Chao authored May 27, 2020
```
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
```
  d4f881d0
- rvv: remove vmlen · 92d41ccb
  Chih-Min Chao authored May 27, 2020
```
vmlen has be changed to 1

Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
```
  92d41ccb
- rvv: op: change funary op · 59aa87bd
  Chih-Min Chao authored May 27, 2020
```
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
```
  59aa87bd
- sf: add f16_to_[u]i8 APIs · 4ece0655
  Chih-Min Chao authored May 27, 2020
```
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
```
  4ece0655
- rvv: handle inactive and NaN case for vfredsum · 21dd7ed0
  Chih-Min Chao authored May 11, 2020
```
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
```
  21dd7ed0
- rvv: disasm: add missing .wx format · ea401070
  Chih-Min Chao authored May 15, 2020
```
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
```
  ea401070
- fix the memory regions checker (#474) · 1edd5a01
  Dave Wen authored May 29, 2020
  
  1edd5a01
May 27, 2020
- Report haltgroup halt cause, per the debug spec. (#473) · 88c87dbb
  Tim Newsome authored May 26, 2020
  
  88c87dbb
May 23, 2020

Make gen_icache script use only POSIX commands (#470) · b7c09621

anthony-coulter authored May 22, 2020



The `seq` utility is not available in OpenBSD.

Co-authored-by: Anthony Coulter <riscv@anthonycoulter.name>

b7c09621

May 21, 2020
- Make sure VLEN/ELEN/SLEN are initialized even without V extension · 667433bb
  Andrew Waterman authored May 20, 2020
  
  667433bb
- Merge pull request #466 from riscv/fix-misa-init · 2364a211
  Andrew Waterman authored May 20, 2020
```
Fix state.misa garbage initialization
```
  2364a211
May 20, 2020
- Fix state.misa garbage initialization · 2d8a9423
  Udit Khanna authored May 19, 2020
  
  2d8a9423
May 19, 2020
- Merge pull request #463 from sbeamer/clang-compile-fix · 513763b5
  Andrew Waterman authored May 18, 2020
```
fix clang compile error within FDT parsing
```
  513763b5
- fix clang compile error wthin FDT parsing · e5dfa01f
  Scott Beamer authored May 18, 2020
  
  e5dfa01f
May 12, 2020
- Merge pull request #461 from riscv/mstatus-spie-sie · a2101111
  Andrew Waterman authored May 12, 2020
```
Hardwire mstatus.[sie,spie] to zero if 'S' mode absent
```
  a2101111
- Hardwire mstatus.[sie,spie] to zero if 'S' mode absent · 47026a21
  Udit Khanna authored May 12, 2020
  
  47026a21
May 10, 2020
- Merge branch 'configurable_PMP' · 9430a823
  Andrew Waterman authored May 10, 2020
  
  9430a823
- Implement coarse-grain PMP matching logic · 0212b6d6
  Andrew Waterman authored May 10, 2020
  
  0212b6d6
- Implement CSR read/write behavior for coarse-grain PMP · 9b579a62
  Andrew Waterman authored May 10, 2020
  
  9b579a62
- Implement configurable PMP count · d5a98bd2
  Andrew Waterman authored May 10, 2020
```
If no PMPs exist, simply deny access to the registers.

If some but not all PMPs exist, the others are hardwired to 0.
```
  d5a98bd2
- Disable PMP checks when configuration includes zero PMP registers · b567da9a
  Andrew Waterman authored May 10, 2020
  
  b567da9a
- Support consuming PMP number and granularity from DTB · 43cfe958
  Andrew Waterman authored May 09, 2020
```
The feature itself isn't implemented yet.
```
  43cfe958
- Rename n_pmp constant to max_pmp · e551131e
  Andrew Waterman authored May 09, 2020
  
  e551131e
May 07, 2020
- Merge pull request #459 from seldridge/stdexcept · 90e67e05
  Andrew Waterman authored May 06, 2020
```
Add missing stdexcept imports (for GCC 10)
```
  90e67e05
- Add missing stdexcept imports · b3855682
  Schuyler Eldridge authored May 06, 2020
```
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
```
  b3855682
May 05, 2020
- Merge pull request #458 from chihminchao/rvv-fp16 · b1de71f4
  Andrew Waterman authored May 04, 2020
```
Rvv fp16
```
  b1de71f4
- parser: fp16: require F extension · cc1e7164
  Chih-Min Chao authored Apr 29, 2020
```
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
```
  cc1e7164
- rvv: fp16: support element movement instructions · 073c8416
  Chih-Min Chao authored Apr 21, 2020
```
vfmv/vfslide/vfmerge

Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
```
  073c8416
- rvv: fp16: support vfwxxx.[wv][vf] instructions · 5ba5c151
  Chih-Min Chao authored Apr 21, 2020
```
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
```
  5ba5c151
- rvv: fp16: support conversion instrucitons · d09689d2
  Chih-Min Chao authored Apr 06, 2020
```
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
```
  d09689d2