- Nov 16, 2023
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Andrew Waterman authored
rs1 doesn't represent a vector arg in this case, so the instructions were broken for (rs1 % ceil(LMUL)) != 0. Resolves #1505
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- Nov 11, 2023
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Tim Newsome authored
Update debug smoketest action.
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Tim Newsome authored
To get https://github.com/riscv-software-src/riscv-tests/pull/522, which fixes an intermittent failure.
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- Nov 10, 2023
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Andrew Waterman authored
fesvr/htif: allow exit on SIGINT.
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- Nov 09, 2023
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Volodymyr Fialko authored
Currently signal handler would call exit() only on second received signal, this prevent proper program cleanup. Instead use signal flag to exit loop. Signed-off-by:Volodymyr Fialko <vfialko@marvell.com>
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Andrew Waterman authored
Add support for setting PMP Granularity over CLI
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- Nov 04, 2023
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Karthik B K authored
PMP Granularity is made available as a command line option. The default value is 4 Bytes. The value can be changed by passing the option --pmp-granularity=<value> to spike. Signed-off-by:Karthik B K <karthik.bk@incoresemi.com>
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- Nov 03, 2023
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Andrew Waterman authored
Add unratified Zabha extension
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Ved Shanbhogue authored
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Ved Shanbhogue authored
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Ved Shanbhogue authored
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Ved Shanbhogue authored
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Ved Shanbhogue authored
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- Oct 31, 2023
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Ved Shanbhogue authored
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- Oct 25, 2023
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Andrew Waterman authored
Fixing minor typo in comment Gallois -> Galois
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- Oct 24, 2023
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Nicolas Brunie authored
Signed-off-by:Nicolas Brunie <82109999+nibrunieAtSi5@users.noreply.github.com>
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- Oct 21, 2023
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Andrew Waterman authored
Adding Zalasr support.
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- Oct 20, 2023
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brs authored
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- Oct 19, 2023
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brs authored
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brs authored
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Andrew Waterman authored
Add unratified Zcmop extension
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- Oct 18, 2023
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Ved Shanbhogue authored
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Andrew Waterman authored
This reverts commit 1de1e819.
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Andrew Waterman authored
add zcmop extension instructions
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Andrew Waterman authored
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Andrew Waterman authored
workflow: Update riscv-openocd and riscv-tests versions
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Tim Newsome authored
Make sure we test with recent OpenOCD and tests.
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Andrew Waterman authored
Remove vector amo
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- Oct 17, 2023
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Chih-Min Chao authored
Signed-off-by:Chih-Min Chao <chihmin.chao@sifive.com>
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Chih-Min Chao authored
Signed-off-by:Chih-Min Chao <chihmin.chao@sifive.com>
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Chih-Min Chao authored
Signed-off-by:Chih-Min Chao <chihmin.chao@sifive.com>
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Chih-Min Chao authored
Signed-off-by:Chih-Min Chao <chihmin.chao@sifive.com>
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- Oct 11, 2023
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Andrew Waterman authored
Update dtm.h with switch_to_* functions
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- Oct 10, 2023
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Abraham Gonzalez authored
Signed-off-by:Abraham Gonzalez <abe.j.gonza@gmail.com>
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- Sep 29, 2023
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Andrew Waterman authored
Fix behavior of unavailable harts.
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Tim Newsome authored
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Tim Newsome authored
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- Sep 28, 2023
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Andrew Waterman authored
Change disasm for vset{i}vli with reserved vtypes to display the reserved bits
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- Sep 27, 2023
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Brendan Sweeney authored
Currently there is a bug with the disassembly when vsetivli/vsetvli have invalid vtypes (with reserved bits set). Spike correctly detects this and sets vill, but the disassembler integrated into spike ignores those bits being set and prints the instruction as if they weren't. This makes debugging harder, it looks like an otherwise valid vtype was being rejected and can lead down debugging paths like thinking the vector unit is configured incorrectly. This commit changes the behaviour so that if these reserved bits are set, it prints out the hex value of the vtype. This is understood by the assembler. GCC disassembler prints out the decimal value of the vtype in this case, I think that hex value is clearer but I can change it if desired. Signed-off-by:Brendan Sweeney <brs@eecs.berkeley.edu>
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- Sep 14, 2023
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Andrew Waterman authored
Hit multiple icount triggers with different actions
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