- Nov 29, 2022
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Tim Newsome authored
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Tim Newsome authored
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Tim Newsome authored
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Tim Newsome authored
chain() -> get_chain() chain_bit -> chain
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YenHaoChen authored
The tdata1.dmode is defined at the same level of tdata1.type. As a result, all triggers has a tdata1.dmode field (even the disabled trigger). With the above consideration, we move the tdata1.dmode checking and setting to the same level of tdata1.type, i.e., in module_t.
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Tim Newsome authored
dmode() -> get_dmode() trigger_t.dmode_bit -> mcontrol_t.dmode
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Tim Newsome authored
store() -> get_store() store_bit -> store
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Tim Newsome authored
load() -> get_load() load_bit -> load
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- Nov 23, 2022
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Tim Newsome authored
execute() -> get_execute(), execute_bit -> execute
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YenHaoChen authored
structuralize trigger's tdata CSRs for modularization
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Scott Johnson authored
Add tinfo register.
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Tim Newsome authored
Not very interesting while spike only supports one trigger type, but #1128 is about to change that. Without tinfo, it can become quite slow for a debugger to discover which types are supported.
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- Nov 22, 2022
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Dylan Reid authored
If a variable other than `i` is passed as `inx`, `VI_LOOP_ELEMENT_SKIP` will still check `i` in the `else` case, ignoring `inx`. Since `i` is the only value ever passed, drop the argument to avoid any future confusion. Signed-off-by:
Dylan Reid <dgreid@rivosinc.com> Signed-off-by:
Dylan Reid <dgreid@rivosinc.com>
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YenHaoChen authored
When resuming from debug mode, clear mstatus.MPRV if the new privilege mode is less than M-mode (#1149)
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- Nov 18, 2022
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Andrew Waterman authored
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Andrew Waterman authored
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Weiwei Li authored
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Weiwei Li authored
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Weiwei Li authored
add suport for jvt: Table entries follow the current data endianness
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Weiwei Li authored
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Weiwei Li authored
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Weiwei Li authored
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Weiwei Li authored
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Weiwei Li authored
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- Nov 17, 2022
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Scott Johnson authored
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Andrew Waterman authored
Do not allow memory regions larger than (1ull << MAX_PADDR_BITS)
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- Nov 16, 2022
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Parshintsev Anatoly authored
Other regions are inaccessible to the hardware being modeled
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- Nov 15, 2022
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Parshintsev Anatoly authored
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- Oct 28, 2022
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Andrew Waterman authored
Fixes #1135
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- Oct 27, 2022
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Scott Johnson authored
Add Spike support for Zvfh and Zvfhmin extensions
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Andrew Waterman authored
fix mevent_mask for Sscofpmf extension
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Scott Johnson authored
fix print message of width=8 accesses
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- Oct 26, 2022
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YenHaoChen authored
The mevent_mask of Sscofpmf depends on the support of privilege modes. The UINH, SINH, VSINH, and VUINH are read-only 0 if unsupporting the corresponding modes. (https://github.com/riscv/riscv-count-overflow/issues/3#issuecomment-1291247070) This commit fixes the mevent_mask of Sscofpmf accordingly. The previous MHPMEVENTH_UINH is a typo, which should be MHPMEVENT_SINH instead.
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Andrew Waterman authored
...as opposed to Zfh.
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Andrew Waterman authored
...as opposed to Zfh.
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Andrew Waterman authored
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Andrew Waterman authored
Clean up dual-endian support
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Jerry Zhao authored
Set target endianess in constructors
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Jerry Zhao authored
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- Oct 21, 2022
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YenHaoChen authored
The number of digits indicates the size of accesses. A size-1 access needs two digits instead of one.
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