update set_msw/clear_msw/set_mtimer/clear_mtimer

Added ifndef to clint addresses instead of hard-coding
Added clear_msw and clear mtimer
Tested against Sail/isa-sim with new proposed Smclint/Ssclint arch-tests
https://github.com/riscv-non-isa/riscv-arch-test/pull/372


Building a baseline of interrupt tests that changes to SAIL/isa-sim can be tested against when other interrupt extensions are added.

Signed-off-by: Dan Smathers <dan.smathers@seagate.com>