Skip to content
GitLab
Projects
Groups
Topics
Snippets
/
Help
Help
Support
Community forum
Keyboard shortcuts
?
Submit feedback
Contribute to GitLab
Sign in
Toggle navigation
Menu
github.com
riscv-software-src
riscv-isa-sim
Commits
bb09cd92
Unverified
Commit
bb09cd92
authored
Sep 25, 2021
by
Scott Johnson
Browse files
Remove unnecessary double-setting of mstatus.FS=Dirty
fflags->write() already sets that.
parent
2b26a3cd
Changes
2
Hide whitespace changes
Inline
Side-by-side
Preview
Supports
Markdown
0%
Try again
or
attach a new file
.
Cancel
You are about to add
0
people
to the discussion. Proceed with caution.
Finish editing this message first!
Save comment
Cancel
Please
register
or
sign in
to comment