* rvp: add 8/16 bits add/sub simd instructions

* rvp: add 8/16 bits shift simd instructions

* rvp: add 8/16 bits compare simd instructions

* rvp: add 8/16 bits multiply simd instructions

* rvp: add 8/16 bits misc simd instructions

* rvp: add 8 bits unpacking simd instructions

* rvp: update suppported extention and add restriction

* rvp: update encoding.h and riscv.mk.in

* rvp: disasm: add simd instruction support

* rvp: update readme for p-ext simd instructions

* rvp: fix rvp support version

* rvp: update encoding.h generated from riscv-opcode p-ext branch

* rvp: rename some macro argument

* rvp: add pk[bb,bt,tt,tb][16,32] instructions

* rvp: add kadd32, [su]maqa[_su] instructions

* rvp: fix missing initial value of pd

* rvp: add msw 32x32 multiply & add instructions

* rvp: change to use extract64

* rvp: add msw 32x16 multiply & add instructions

* rvp: fix some style

* rvp: change reduction marcro definition

* rvp: add signed 16x32 add/subtract instructions

* rvp: use stdint to replace hardcode max/minimum

* rvp: refactor some p-ext macro code

* rvp: add partial simd miscellaneous instructions

* rvp: add signed 16 x 64 add/subtract Instructions

* rvp: add 64-bit add & sub instructions

* rvp: add 32-bit mul with 64-bit add/sub instructions

* rvp: add 16-bit mul with 64-bit add/sub instructions

* rvp: disasm: add 64 bit profile instruction support

* rvp: add Q15 saturation instructions

* rvp: fix kmar64/kmsr64 saturation behavior

* rvp: add 32-bit computation instructions

* rvp: add rdov/clrov and fix khm16 behavior of setting OV flag

* rvp: add non simd miscellaneous instructions

* rvp: add Q31 saturation instructions

* rvp: disasm: add non-simd instruction support

* rvp: add 32 bits add/sub simd instructions

* rvp: fix left shift saturation bug

* rvp: add 32 bits shift simd instructions

* rvp: add rv64 only Q15 simd instructions

* rvp: add rv64 only 32-bit multiply instructions

* rvp: add rv64 only 32-bit miscellaneous instructions

* rvp: add rv64 only 32-bit mul & add instructions

* rvp: add rv64 only 32-bit parallel mul & add instructions

* rvp: add rv64 only non-simd 32-bit shift instructions

* rvp: disasm: remove redundant tab

* rvp: disasm: add rv64 only instructions support

* rvp: change ov csr to ucode to match v0.5.2 spec

* rvp: update readme for p-ext 0.5.2

* rvp: update to p-ext v0.9.1

* rvp: update to p-ext v0.9.2

* rvp: update readme for p-ext 0.9.2

* rvp: fix macro for PKxx16 & PKxx32 commands.

* rvp: fix missing for in PKxxdd macro

* Sign-extension for p-ext insns

* * Fixed uclipNN insns while sh >> 64 is an UB.
* Added missing OV
* Added missing sext_xlen

* Remove unused macroses

* Sign extension for RD_PAIR macro

* rvp: remove lost tab

Co-authored-by: Mark Fedorov <mark.fedorov@cloudbear.ru>