Implement a lock enabled iteration for fifo so that
caller can determine if next entry can be skipped or
any existing entries in fifo can be updated before enqueue.

Signed-off-by: Atish Patra <atish.patra@wdc.com>

This patch extends our current build-system for building platform
sources which are not part of OpenSBI sources.

For example:

Let's say we have out-of-tree ABC platform sources. We place these
sources under <XYZ>/ABC directory along with its config.mk and
objects.mk.

To build out-of-tree ABC platform from OpenSBI directory:
$ make PLATFORM_DIR=<XYZ>/ABC
OR
$ make PLATFORM_DIR=<XYZ> PLATFORM=ABC

To build out-of-tree ABC platform from <XYZ>/ABC directory:
$ make PLATFORM_DIR=<XYZ>/ABC -C <path_to_opensbi>
OR
$ make PLATFORM_DIR=<XYZ> PLATFORM=ABC -C <path_to_opensbi>

Signed-off-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>

Fix the ECALL definitions to matc the latest information in the
privlidge spec table 5.5.

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>

When I tried to start opensbi with coreboot, I found that aligning to a 16-byte
boundary would make a copy error.

Corrected to align to an machine word length boundary.

Signed-off-by: Xiang Wang <wxjstz@126.com>

This patch reduces memory consumed by struct sbi_fifo by droping
redundant "head" member and using u16 in-place of "unsigned long".

Signed-off-by: Anup Patel <anup.patel@wdc.com>

This patch does following improvements to sbi_fifo:
1. Use valid SBI_Exxxx error codes instead of -1
2. The sbi_fifo_is_full() and sbi_fifo_is_empty() did
   not acquire qlock before accessing head and tail
   hence fixed it
3. Added avail member for ease in debugging and simplifying
   head/tail updates.

Due to above changes size of sbi_fifo changes from 48 bytes
to 56 bytes.

Signed-off-by: Anup Patel <anup.patel@wdc.com>

We now have an OpenSBI mailing list available for development
and discussiong so update contributing.md accordingly. The
Github PR based review and issue tracking will also continue
to exist.

Signed-off-by: Anup Patel <anup.patel@wdc.com>

Currently, there is no provision for tracking multiple IPIs sent
to a single hart at the same time by different harts.

Use a fifo manage the outstanding requests. While dequeueing, read all
the entries once, because we have only 1 bit to track the type of IPI.
Once the queue is full, busy wait until the there is space available in
queue. This is not the most elegant approach. It should be changed in
favor of a wakeup event once available in opensbi.

Signed-off-by: Atish Patra <atish.patra@wdc.com>

Currently scratch space per hart is 256 bytes. Increase it to 512 bytes
to accomodate ipi queue.

Signed-off-by: Atish Patra <atish.patra@wdc.com>

Add a tlb info to distinguish between different type of tlb flush
request pending.

Signed-off-by: Atish Patra <atish.patra@wdc.com>

Implement a fifo to accomodate outstanding IPIs for a specific hart
at the same time.

Signed-off-by: Atish Patra <atish.patra@wdc.com>

Add missing SPDX and copyright information.

Signed-off-by: Damien Le Moal <damien.lemoal@wdc.com>

Add information regarding the Apache License Version 2.0 of some of the
Kendryte/k210 platform files. Also repeat this information in a new
ThirdPartyNotices.md file.

Signed-off-by: Damien Le Moal <damien.lemoal@wdc.com>

The mstatus parameter of get_insn() is used to return MSTATUS CSR
value which get_insn() saw. Most of the get_insn() callers don't
use the value returned in mstatus so this patch makes mstatus
parameter optional for get_insn().

Signed-off-by: Anup Patel <anup.patel@wdc.com>

The sbi_unpriv.h has quite a few load_xyz() and store_xyz() helper
routines based on RISC-V inline assembly for unpriviledged accesses
from M-mode. These helper routines are similar to helper routines
present in riscv_locks.h, riscv_io.h, and riscv_atomic.h so let's
rename sbi_unpriv.h to riscv_unpriv.h.

Signed-off-by: Anup Patel <anup.patel@wdc.com>

This patch removes unused mepc arg from load_xyz() and store_xyz()
unpriviledge access functions.

Signed-off-by: Anup Patel <anup.patel@wdc.com>

Use the newly introduced "options" in "struct sbi_scratch" to
conditionally disable the boot prints.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>

Refactor the codes a little bit to put all prints during boot into
sbi_boot_prints().

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>

Introduce "options" in "struct sbi_scratch" and firmware can update
it based on optional compile time flags before calling sbi_init().

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>

The codes that currently program the interrupt enable register for
S-mode disagrees with what the comments say. Fix the comments.

While we are here, add one line comment to describe what is done
for M-mode too.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>

OpenSBI should show error trace only if any valid SBI function
does not perform as expected.

However, OpenSBI should show notify the caller with a negative
error if given SBI function ID is not valid.

Signed-off-by: Atish Patra <atish.patra@wdc.com>

Per PLIC spec, interrupt ID 0 is defined to mean "no interrupt".
We should bypass it.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>

At present plic_set_priority() ignores the 'source' and the priority
register to be programmed is constant. Fix it.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>

Scratch space setup needs to be done once for reboot for each
hart. _start_warm may be called several times if hart hotplug
is implemented.

Move scratch space setup to the beginning so that it is done
only once.

Signed-off-by: Atish Patra <atish.patra@wdc.com>

Currently, global page mappings are not flushed if start and size
arguments are zero.

Flush entire TLB if both size and start argument is passed as zero.

Fixes : 90cb4917

 (lib: Implement sfence.vma correctly)

Signed-off-by: Atish Patra <atish.patra@wdc.com>

There are some spaces or mixed usage of spaces and tabs in the macro
definition. Change to use tab consistently.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>

It's U-Boot, not U-boot.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>

Currently, OpenSBI doesn't distinguish between sfence.vma
and sfence.vm asid calls. Moreover, it ignores the page
ranges and just flush entire TLB everytime.

Fix the sfence implementation by keeping all the tlb flush
info in scratch area.

The relevant Linux kernel code was added by
https://patchwork.kernel.org/project/linux-riscv/list/?series=89695



However, this patch is backward compatible with older version kernel
that doesn't have the above patches as well.

Fixes #87
Signed-off-by: Atish Patra <atish.patra@wdc.com>

Create a sbi_ipi_data structure that holds unpacked IPI information. At
the same time remove ipi_type from the sbi_scratch struct and use a
fixed offset to access it.

This structure fits in behind the sbi_scratch structure.

This fixes https://github.com/riscv/opensbi/issues/81



Signed-off-by: Alistair Francis <alistair.francis@wdc.com>

A warm reset using reset button may put icache and registers
in non-coherent state.

Flush the icache and reset all registers for every hart.

Signed-off-by: Atish Patra <atish.patra@wdc.com>

All the non-boot harts run in a tight loop which may cause a heavy load
on the memory bus. This may delay the boot hart to complete the cold boot
process.

Introduce few nop that will ease up the traffic.

Signed-off-by: Atish Patra <atish.patra@wdc.com>

This reverts commit 05602e2b.

Introducing a fence causes warm reset issue to reappear. Revert it
for the time being.

platform should be a read-only variable, if it is placed in the data
segment, it may be exploited.

Signed-off-by: Xiang Wang <wxjstz@126.com>

A warm reset by pressing the reset button may not initialize all the
registers to zero. Do it for every hart during warm boot.

Signed-off-by: Atish Patra <atish.patra@wdc.com>

Signed-off-by: Atish Patra <atish.patra@wdc.com>

Signed-off-by: Atish Patra <atish.patra@wdc.com>

As per the current SBI specification, sbi_getc should return
an int instead of char.

In case of FIFO is empty, return -1 as per the specification.

Reported-by: Sergi Granell <xerpi.g.12@gmail.com>
Suggested-by: Thadeu Lima de Souza Cascardo <cascardo@cascardo.eti.br>
Signed-off-by: Atish Patra <atish.patra@wdc.com>

Multi-core communication via memory requires the addition of a barrier
instructions to ensure cache coherency.

Signed-off-by: Xiang Wang <wxjstz@126.com>

Writable code section can cause some security problems, so move _boot_hart_done
to the data section

Signed-off-by: Xiang Wang <wxjstz@126.com>

Signed-off-by: Xiang Wang <wxjstz@126.com>