The information parsed by fdt_parse_uart8250() API is not complete.
We need to parse reg-shift and reg-io-width for UART 8520 as well.

Signed-off-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Atish Patra <atish.patra@wdc.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>

We should skip baudrate config for UART8250 and SiFive UART when
input frequency is zero.

Signed-off-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Atish Patra <atish.patra@wdc.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>

Remove unnecessary CSR_MTVEC read to reduce the openSBI CSR requirement.

Mux are costly in FPGA. Allowing CSR_MTVEC to be write only is usefull
for the FMax/Area of FPGA softcore.

https://github.com/SpinalHDL/opensbi.git

 branch mtvec

Signed-off-by: Charles Papon <charles.papon.90@gmail.com>
Reviewed-by: Atish Patra <atish.patra@wdc.com>
Reviewed-by: Anup Patel <anup.patel@wdc.com>

Signed-off-by: Huaqi Fang <578567190@qq.com>
Reviewed-by: Anup Patel <anup.patel@wdc.com>

* Nuclei UX600 is a 64-bit RISC-V core developed
  by Nuclei System Technology, see https://nucleisys.com/product.php



* The ISA is configurable in hardware on your demand

Signed-off-by: Huaqi Fang <578567190@qq.com>
Reviewed-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

This patch factor-out SiFive test device related stuff into
it's own source file from qemu/virt platform. In future, we
can find SiFive test device address from device tree as well.

Signed-off-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Atish Patra <atish.patra@wdc.com>

We can achieve shutdown, cold reboot, and warm reboot using just
one sbi_platform callback so we combine system_reboot() and
system_shutdown() callbacks into one system_reset() callback.

Signed-off-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Atish Patra <atish.patra@wdc.com>

The default (usually last) PMP region provides S-mode access to
complete memory range not covered by other PMP regions.

Currently, the default PMP region is described as platform specific
PMP region which is not appropriate because all platforms need it
and default PMP region should be part of generic library.

Signed-off-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Atish Patra <atish.patra@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

This patch updates OpenSBI version to 0.7 as part of
release preparation.

Signed-off-by: Anup Patel <anup.patel@wdc.com>

Ideally, the SBI implementation ID for OpenSBI should always be
0x1 (as mentioned in SBI v0.2 spec) but external firmware (such
as EDK2) which use OpenSBI as library might want to override the
SBI implementation ID with their custom implementation ID.

Signed-off-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Atish Patra <atish.patra@wdc.com>

Signed-off-by: Atish Patra <atish.patra@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Anup Patel <anup.patel@wdc.com>

Enable vector context in mstatus by updating the corresponding bits
in mstatus if vector extension is supported by the hart.

Signed-off-by: Atish Patra <atish.patra@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Anup Patel <anup.patel@wdc.com>

As per the PLIC specification, maximum priority threshold value is 0x7.
Even though, writing a higher value doesn't cause any error in qemu
hifive unleashed, there may be some implementation which checks the upper
and may result in an illegal access.

Signed-off-by: Atish Patra <atish.patra@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Anup Patel <anup.patel@wdc.com>

Remove custom vendor extension and use HSM extension
to boot secondary cores

Signed-off-by: Liu Yibin <yibin_liu@c-sky.com>
Reviewed-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

This patch removes scratch parameter from sbi_dprintf() function
because sbi_dprintf() can use sbi_scratch_thishart_ptr() to get
current HART scratch space.

Signed-off-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Atish Patra <atish.patra@wdc.com>

This patch removes scratch parameter from most sbi_timer functions.

Signed-off-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Atish Patra <atish.patra@wdc.com>

This patch removes scratch parameter and redundant functions from
sbi_system.

Signed-off-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Atish Patra <atish.patra@wdc.com>

This patch removes scratch parameter from most sbi_ipi functions.

Signed-off-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Atish Patra <atish.patra@wdc.com>

The sbi_ipi_send_many() should get current HART scratch pointer
on it's own using eventually hence removing scratch parameter from
sbi_tlb_request().

Signed-off-by: Anup Patel <anup.patel@wdc.com>

The patch adds sbi_scratch_last_hartid() API which returns
last HART id having a scratch space. We can use this new API
to optimize places where we iterate over HART id from 0 to
SBI_HARTMASK_MAX_BITS.

Signed-off-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Atish Patra <atish.patra@wdc.com>

We should remove the "arch_" prefix from atomic xchg() and cmpxchg()
function names to have consistent naming of all atomic functions.

Signed-off-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Atish Patra <atish.patra@wdc.com>

The priv parameter in hart_start() platform callback is redundant hence
we remove it.

Signed-off-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Atish Patra <atish.patra@wdc.com>

This patch simplify sbi_trap_handler() API as follows:
1. Remove current hartid local variable because sbi_trap_handler()
   itself does not need it.
2. Remove scratch parameter because none of the functions directly
   called by sbi_trap_handler() require it.

Signed-off-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Atish Patra <atish.patra@wdc.com>

We remove mcause, scratch and hartid parameters from various
functions for ecall handling because we can always get current
HART id and current scratch pointer using just one CSR access.

Signed-off-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Atish Patra <atish.patra@wdc.com>

We remove mcause, scratch and hartid parameters from various functions
for misaligned load/store handling because we can always get current
HART id and current scratch pointer using just one CSR access.

Signed-off-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Atish Patra <atish.patra@wdc.com>

We remove mcause, scratch and hartid parameters from various
functions for illegal instruction handling because we can always
get current HART id and current scratch pointer using just one
CSR access.

Signed-off-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Atish Patra <atish.patra@wdc.com>

We remove scratch and hartid parameter from various functions
for CSR emulation because we can always get current HART id
and current scratch pointer using just one CSR access.

Signed-off-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Atish Patra <atish.patra@wdc.com>

The scratch parameter of sbi_trap_redirect() is not used hence we
remove it.

Signed-off-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Atish Patra <atish.patra@wdc.com>

The scratch parameter of unpriv load/store functions is now redundant
hence we remove it.

Signed-off-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Atish Patra <atish.patra@wdc.com>

This patch optimize unpriv load/store implementation by having
dedicated unpriv trap handler (just like KVM RISC-V).

As a result of this optimization:
1. We have reduced roughly 13+ instruction in all unpriv load/store
   functions. The reduced instruction also include two function calls.
2. Per-HART trap info pointer in scratch space is now redundant
   hence removed.
3. The sbi_trap_handler() is now much cleaner because we don't have
   to handle unpriv load/store traps.

Signed-off-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Atish Patra <atish.patra@wdc.com>

Currently, the fdt_cpu_fixup() implementation assumes:
1. We have one CPU DT for each HART under /cpus DT node
2. The CPU DT nodes are named sequentially (i.e cpu@0,
   cpu@1, ...) which is not true for discontinuous and
   sparse HART ids (i.e. cpu@0, cpu@4, cpu@5). Generally,
   CPU DT node are named based on HART id and not HART
   index

If any of the above assumptions are violated then the
fdt_cpu_fixup() will not work.

This improves fdt_cpu_fixup() implementation and makes
it independent of above assumptions.

Signed-off-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Atish Patra <atish.patra@wdc.com>

This patch extends/revamps create-binary-archive.sh to allow creating
unified binary tar ball containing both RV32 and RV64 images. Users
can also create "RV32 only" or "RV64 only" tar balls as well.

Few example commands are as follows:
./scripts/create-binary-archive.sh (Build both RV32 & RV64 images)
./scripts/create-binary-archive.sh -x 32 (Build RV32 only images)
./scripts/create-binary-archive.sh -x 64 (Build RV64 only images)

Signed-off-by: Anup Patel <anup.patel@wdc.com>

HSM_STOP will trigger multiple executions of sbi_init, atomic_add_return may
trigger coldboot_lottery overflow

Signed-off-by: Xiang Wang <merle@hardenedlinux.org>
Reviewed-by: Anup Patel <anup.patel@wdc.com>

OpenPiton is designed to run on different FPGAs with different
configurations. Use the fdt parser to retrieve the required values
from device tree instead of using fixed values.

Signed-off-by: Atish Patra <atish.patra@wdc.com>
Tested-by: Jonathan Balkind <jbalkind@cs.princeton.edu>
Reviewed-by: Anup Patel <anup.patel@wdc.com>

FDT helper file contain both fdt fixup and parsing functions.

Split the fixup related functions to a separate file for a better code
organization.

Signed-off-by: Atish Patra <atish.patra@wdc.com>
Reviewed-by: Anup Patel <anup.patel@wdc.com>

Different DT based platforms from the sam family may reuse IP blocks with
different configurations. These different configurations can be obtained
by parsing the device tree.

Add a FDT parser framework that can parse various device configurations from
device tree. Currently, the parsing algorithms doesn't cover all the use cases
or possible combination of DT configurations. It will be improved over time.

Signed-off-by: Atish Patra <atish.patra@wdc.com>
Reviewed-by: Anup Patel <anup.patel@wdc.com>

OpenPiton is a research platform from Princeton University [1].

"OpenPiton is the world's first open source, general purpose,
multithreaded manycore processor. It is a tiled manycore
framework scalable from one to 1/2 billion cores."

Add OpenSBI support for OpenPiton. As it is based on ariane core,
it reuses the platform code from arine project.

[1]. https://github.com/PrincetonUniversity/openpiton



Signed-off-by: Atish Patra <atish.patra@wdc.com>
Reviewed-by: Anup Patel <anup.patel@wdc.com>

All the common PLIC specific macros are already defined in plic.c.

Remove it from platform code. While at it, Fix the other coding style
issues.

Signed-off-by: Atish Patra <atish.patra@wdc.com>
Reviewed-by: Anup Patel <anup.patel@wdc.com>

Signed-off-by: Atish Patra <atish.patra@wdc.com>
Reviewed-by: Anup Patel <anup.patel@wdc.com>

Commit 71d2b837 (lib: Move all coldboot wait APIs to sbi_init.c)
caused a regression while moving the code from sbi_hart.c to sbi_init.c.

As per original commit text, WFI can be implemented as a NOP according
to the RISC-V privilege specification. Software should ensure that
relevant interrupt pending bits are set. Otherwise, loop back to WFI.
Fix the regression by applying the original patch to sbi_init.c.

Fixes: 71d2b837

 ("lib: Move all coldboot wait APIs to sbi_init.c")

Signed-off-by: Atish Patra <atish.patra@wdc.com>
Reviewed-by: Anup Patel <anup.patel@wdc.com>