Similar to #38, riscv compilers may also generate 'small ro data' `.srodata` sections.

This doesn't appear to be well documented, but see [this blog post](https://www.sifive.com/blog/all-aboard-part-3-linker-relaxation-in-riscv-toolchain) for small amount of context.

38: link.x: Add .sdata2 sections r=Disasm a=laanwj

Clang doesn't seem to generate these, but GCC (8.3.0 at least) does. I'm trying to link secp256k1, which is a C library, to my Rust code so the linker script needs to include these sections too.

Co-authored-by: Wladimir J. van der Laan <laanwj@gmail.com>

Clang doesn't seem to generate these, but GCC does. I'm trying to
link secp256k1, which is a C library, to my Rust code so the linker
script needs to include these sections too.

37: Fix _start_trap save/restore sequences r=laanwj a=Disasm



Co-authored-by: Vadim Kaushan <admin@disasm.info>

36: Fix linker script r=laanwj a=Disasm

This PR fixes
* section alignment issues
* section flags (now both `.heap` and `.stack` are `NOBITS`)
* wrong offsets with overridden `_stext`

Co-authored-by: Vadim Kaushan <admin@disasm.info>

35: Add .sbss section to linker script r=Disasm a=laanwj

Rust nightly has started generating this section for RISC-V executables, place it at the start of the bss area.

```
  = note: rust-lld: error: no memory region specified for section '.sbss'
```

I think this is correct, looking at other uses of the section, though I could find no definitive documentation for this.

Co-authored-by: Wladimir J. van der Laan <laanwj@gmail.com>

Rust nightly has started generating this section for RISC-V executables,
place it at the start of the bss area.

31: New linker script and multi-core support r=laanwj a=Disasm

* Linker script was reworked. Now it uses region aliases to relocate sections. This approach makes it possible to build firmware for both FLASH+RAM and RAM-only targets. Memory definitions now supposed to be present in their corresponding crates (e.g. RAM definition in PAC crate, FLASH definition in board support crate).
* Multi-core support was introduced. Cores are parked with `_mp_hook` function and then awakened in platform-dependent way.
* Documentation was updated to reflect new features.
* New crate version: 0.6.0

Depends on: https://github.com/rust-embedded/riscv/pull/28
Closes: https://github.com/rust-embedded/riscv-rt/issues/26



Co-authored-by: Vadim Kaushan <admin@disasm.info>

32: Rename RISCV to RISC-V r=laanwj a=Disasm

The same as here: https://github.com/rust-embedded/riscv/pull/25



Co-authored-by: Vadim Kaushan <admin@disasm.info>

This reverts commit 3a76c3b2.