features: adds `rt` feature for gd32vf103-pac/rt

Adds a `rt` feature to allow users to opt-in to using the
`gd32vf103-pac/rt` feature. This exposes the `interrupt` macro, allowing
users to define functions for system interrupts.

This is preferable to using inline assembly to include the code in
`eclic-mode-hack.S` which causes symbol collisions with user-defined
interrupt functions, and strange bugs for handler execution.

Fix unsatisfied bound

Bump version and note changes in CHANGELOG.md

Add ADC driver

Restrict pwm to channel

The PWM duty cycle could be changed on-the-fly. It is not necessary to disable
and then enable the channel.

That avoid some "missing" PWM cycle during the change.

Now enabling the channel explicitly is mandatory to get an output.

Fix #30

On GD32V103f there is 4 types of remaps for PWM. Not all timers are able to be
configured with this 4 remaps types. Also it is not possible to deduce the
Remap type with the pins used (e.g TIMER0).

The implementation works with an intermediate trait Pins<TIMER, REMAP> which is
implemented for all compatibles tuples of gpio::P** for the specified couple
TIMER, REMAP.

```rust
    // ...

    let mut pwm_t0 = PwmTimer::<TIMER0, NoRemap>::new(
        timer0, (None, Some(&pa9), Some(&pa10), None), &mut rcu, &mut afio
    );

    // ...
    pwm_t0.set_duty(Channel::CH1, 100);

```

Add CHANGELOG.md file

Replaced unreachable!() with panic!()

Added Spi::change_clock_frequency()

Add support for DMA

Port I2C fixes from STM32F1xx HAL.

Use cchp.oaen bit to enable automatically all TIMER0 PWM channels.

For advanced timers, an additional bit needs to be set to enable all outputs
(CCPH.POEN). This bit is used handle the break function.

Here we use the CCHPH.OAEN bits which allow automatic modification of POEN.

Add exti support

Exti for configuring external interrupt from GPIO pins as well as some
interrupt sources coming from other peripherals (LVD, RTC, USB)

`extiss()` added in Afio for configuring exti source selction register