version update

Signed-off-by: Umer Shahid <umer.shahid@10xengineers.ai>

Add ratified Zcmop extension

Updated Changelog file to remove versioning issues

Signed-off-by: Umer Shahid <umer.shahid@10xengineers.ai>

Add ratified Zimop extension

Updated Changelog entry to resolve versioning issues and conflicts

Signed-off-by: Umer Shahid <umer.shahid@10xengineers.ai>

Add ratified Svadu extension

Updated Changelog file to remove version conflicts

Signed-off-by: Umer Shahid <umer.shahid@10xengineers.ai>

Forced changes to resolve the conflicts

Signed-off-by: Umer Shahid <umer.shahid@10xengineers.ai>

Signed-off-by: Umer Shahid <umer.shahid@10xengineers.ai>

Add ratified Zacas extension

Updated Changelog file to resolve conflict

Signed-off-by: Umer Shahid <umer.shahid@10xengineers.ai>

Signed-off-by: Umer Shahid <umer.shahid@10xengineers.ai>

Add support for the Zfa ISA extension

Added new entry in Changelog and resolved conflicts

Signed-off-by: Umer Shahid <umer.shahid@10xengineers.ai>

Signed-off-by: Umer Shahid <umer.shahid@10xengineers.ai>

Split rv32i_m/F/fnmadd_b15.S, fnmsub_b15.S, fmadd_b15.S, fmsub_b15.S into multiple smaller tests

Added missing .*32 in rv32i_m/C/src/clh-01.S

Fix: RVTEST_CASE missing ISA

[flh-align-01] fix ISA config in RVTEST_CASE macro

Signed-off-by: stnolting <stnolting@gmail.com>

Signed-off-by: stnolting <stnolting@gmail.com>

Signed-off-by: Allen Baum <31423142+allenjbaum@users.noreply.github.com>

Signed-off-by: stnolting <stnolting@gmail.com>

This patch introduces the RISC-V Zfa extension, which introduces
additional floating-point extensions:
* fli (load-immediate) with pre-defined immediates
* fminm/fmaxm (like fmin/fmax but with different NaN behaviour)
* fround/froundmx (round to integer)
* fcvtmod.w.d (Modular Convert-to-Integer)
* fmv* to access high bits of float register bigger than XLEN
* Quiet comparison instructions (fleq/fltq)

Zfa defines its instructions in combination with the following
extensions:
* single-precision floating-point (F)
* double-precision floating-point (D)
* quad-precision floating-point (Q)
* half-precision floating-point (Zfh)

Since the RISC-V architecture test framework does not support
the RISC-V quad-precision floating-point ISA extension (Q) and
the RISC-V half-precision floating-point ISA extension (Zfh),
this patch does not include tests for instructions that depend
on these extensions.

Given missing infrastructure support, the fli.* instruction tests
are hand written and not generated.
All other test files are generated using riscv-ctg.

The generated test files have been generated using the following
command (with $BASEISA={rv32i,rv64i}, $FLEN={32,64}), and CFG=$INSN:
      riscv_ctg.py \
        --cgf sample_cgfs/dataset.cgf \
        --cgf sample_cgfs/zfa/$CGF \
        --base-isa $BASEISA \
        --flen $FLEN \
        -d tests_$BASEISA_$FLEN/

Exceptions are:
* fcvtmod.w.d.cgf is for FLEN=32 only
* fmvh.x.d and fmvp.d.x are for BASEISA=rv32i only

The resulting tests have been copied to the target directory.

The generation of the Zfa test cases depends on a PR in the riscv-ctg
repository:
  https://github.com/riscv-software-src/riscv-ctg/pull/60

The Zfa specification is ratified and can be found here:
  https://github.com/riscv/riscv-isa-manual/blob/main/src/zfa.adoc



Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>

Fized Zfh fcvt RVTEST_CASE macros