- Nov 08, 2023
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Tim Newsome authored
The existing code didn't seem to work right at all. I have spike modifications that exercise these new cases. I'll merge those once this has merged. Change-Id: I89bd336f34f1b208a76f25b6b41fe3877800765b Signed-off-by:Tim Newsome <tim@sifive.com>
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- Nov 07, 2023
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Tim Newsome authored
target/riscv: gdb_regno_name takes an enum.
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- Nov 04, 2023
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Tim Newsome authored
Otherwise it won't compile for me. Not sure why that doesn't affect the automated builds. Change-Id: Ic66c743e1698c4c0772e5601723cb5c711b4fa5c Signed-off-by:Tim Newsome <tim@sifive.com>
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Tim Newsome authored
target/riscv: Adding register tables to make register names consiste
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Tim Newsome authored
From upstream
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- Nov 03, 2023
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Tim Newsome authored
target/riscv: Fix memory access when MMU is enabled and address couldn't be translated
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- Nov 02, 2023
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Anastasiya Chernikova authored
Added the ability to enter dimensionless registers Change-Id: I1b781959ce4690ec65304142bd9a7c6f540b3e86 Signed-off-by:Anastasiya Chernikova <anastasiya.chernikova@syntacore.com>
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Tim Newsome authored
Remove mention of esp32c2, esp32c3 from doc
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- Nov 01, 2023
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Tim Newsome authored
Remove mention of "riscv set_scratch_ram" from doc
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Tim Newsome authored
target/riscv: Prevent dump_field() reading uninitialized memory
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Jan Matyas authored
This command no longer exists, was removed in: https://github.com/riscv/riscv-openocd/commit/ead2a595b8491ed48ce2ced81d2935dc8a4c4973 Remove it from the doc as well. Signed-off-by:
Jan Matyas <jan.matyas@codasip.com>
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- Oct 31, 2023
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Jan Matyas authored
Targets "esp32c2" and "esp32c3" should not be mentioned in the doc under "target types" because these are not standalone OpenOCD targets. They are merely a set of .cfg files which use the generic "riscv" target. Signed-off-by:Jan Matyas <jan.matyas@codasip.com>
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Tim Newsome authored
Change-Id: I9ef8f2c2e9a824aa6595e8f20682c968ae5aed72 Signed-off-by:Tim Newsome <tim@sifive.com>
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- Oct 30, 2023
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Tim Newsome authored
Removed deprecated gd32vf103_flash
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Kirill Radkin authored
Now: 1) If mmu is disabled, virt2phys succeeded and returns physical address 2) If mmu is enbaled, but translation fails, read/write_memory fails Change-Id: I312309c660239014b3278cb77cadc5618de8e4de Signed-off-by:Kirill Radkin <kirill.radkin@syntacore.com>
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Jan Matyas authored
Removing flash driver "gd32vf103_flash". This driver has been deprecated since June-1-2022, and was scheduled for removal in June 2023. Change-Id: Ib6f4dcba11e91a095b3a20eedd864589084b7fa9 Signed-off-by:Jan Matyas <jan.matyas@codasip.com>
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- Oct 28, 2023
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Tim Newsome authored
Conflicts: HACKING src/target/riscv/riscv-013.c Change-Id: I43ccb143cae8daa39212d66a8824ae3ad2af6fef
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- Oct 27, 2023
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Tim Newsome authored
From upstream
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Tim Newsome authored
Remove an extra call to kept_alive()
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Tim Newsome authored
target/riscv: update debug register printers
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- Oct 26, 2023
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Evgeniy Naydanov authored
Change-Id: I069bbe069a3aaa7fd3a4f6eccde40f813db33cc9 Signed-off-by:Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
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- Oct 25, 2023
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Jan Matyas authored
This incorrect extra call has been removed in upstream code already in March 2022, see https://review.openocd.org/c/openocd/+/6836 . Remove it from riscv-openocd as well. Change-Id: Ie341f5578c8bfdc518adf1e4bc134919ab76f803 Signed-off-by:
Jan Matyas <jan.matyas@codasip.com>
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- Oct 24, 2023
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Tim Newsome authored
hgatp_mode in riscv_virt2phys_v defined by vsatp value
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Tim Newsome authored
Change-Id: I20bd0356c63745423e23aec71f272fe2e32db88e Signed-off-by:Tim Newsome <tim@sifive.com>
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Tim Newsome authored
Conflicts: src/flash/nor/drivers.c src/target/riscv/riscv.c Change-Id: Ide3eded7e0d5b0b446bfd0873a32c00cc9f128bd
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Tim Newsome authored
Revert "target/riscv: Reject size 2 soft breakpoints when C extension not supported"
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- Oct 23, 2023
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Kirill Radkin authored
Replace `vsatp` with `hgatp` (how it should be) Change-Id: Ie548467b06d1fb266ccc56cbec1aff8d9f435973
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Tim Newsome authored
Merge down up to 0384fe5d from upstream.
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- Oct 21, 2023
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Tim Newsome authored
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- Oct 19, 2023
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Tim Newsome authored
contrib: Match upstream.
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Tim Newsome authored
flash/stm32lx: Revert to upstream version.
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Tim Newsome authored
Remove end-of-line whitespace.
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- Oct 18, 2023
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Tim Newsome authored
Reintroduce checkpatch problem, because now we can handle them better. Change-Id: Ib81b9910433ae1a240630b898edb19da8d2d5d83 Signed-off-by:Tim Newsome <tim@sifive.com>
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Tim Newsome authored
Upstream has a checkpatch failure here. I had fixed it because I didn't know how else to properly get around it back then. Reintroduce the problem. Now this file is identical to upstream. Change-Id: Ic03b6bb42945ddbcfd2fe12c0cab5b05eda1a50c Signed-off-by:Tim Newsome <tim@sifive.com>
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Tim Newsome authored
Revert "target: Update messages connected with `examine`"
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- Oct 17, 2023
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Kirill Radkin authored
This reverts commit a3db93b1. Reason for revert: https://github.com/riscv/riscv-openocd/pull/931#issuecomment-1761550506
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Tim Newsome authored
Change-Id: I0deffafe954abaaa4c593896a2d781c2fa00eef2 Signed-off-by:Tim Newsome <tim@sifive.com>
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Tim Newsome authored
At change 0384fe5d . Change-Id: I1081e09f1014c5d240988fc25feba04fc2bb21ef Signed-off-by:
Tim Newsome <tim@sifive.com>
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Tim Newsome authored
Conflicts: .github/workflows/snapshot.yml src/rtos/FreeRTOS.c Change-Id: I4c9ff887b69140e0f61cb3f75a2f2c1a12071320 -
Tim Newsome authored
do not assume DTM version unless dtmcontrol is read successfully
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