gcc/ChangeLog

2018-01-02  Kito Cheng  <kito.cheng@gmail.com>

	* riscv/riscv-protos.h (riscv_output_return): New function.
	* config/riscv/riscv.c (machine_function): New naked_p field.
	  (riscv_attribute_table): Add table for target-specific attribute.
	  (riscv_output_return): Handle naked function.
	  (riscv_naked_function_p): Ditto.
	  (riscv_allocate_stack_slots_for_args): Ditto.
	  (riscv_warn_func_return): Ditto.
	  (riscv_compute_frame_info): Ditto.
	  (riscv_expand_prologue): Ditto.
	  (riscv_expand_epilogue): Ditto.
	  (riscv_set_current_function): Ditto.
	* config/riscv/riscv.md (simple_return): Call
	  riscv_output_return for handle naked function.
	* doc/extend.texi: Document naked attribute for RISC-V.

  - When a leaf function compile with save-restore routine, prologue and
    epilogue will miss match.

gcc/ChangeLog

2017-01-03  Monk Chiang  <sh.chiang04@gmail.com>
	    Kito Cheng  <kito.cheng@gmail.com>

	* config/riscv/riscv.c (machine_function::is_leaf): Remove
	  field.
	  (machine_function::use_save_libcall_p): New field.
	  (riscv_expand_prologue): Set machine_function::use_save_libcall_p.
	  (riscv_leaf_function_p): Delete.
	  (riscv_function_ok_for_sibcall): Use
	  machine_function::use_save_libcall_p instead of
	  machine_function::is_leaf to check sibcall is ok.

gcc/testsuite/ChangeLog

2018-01-03  Chih-Mao Chen <pkmx.tw@gmail.com>
	    Monk Chiang  <sh.chiang04@gmail.com>

	* gcc.target/riscv/save-restore-1.c: New test.

Rewrite multi3.c with faster implementation.

Add -mabi=ilp32e

The fence.i instruction is not appropriate, because it only flushes
the current core's I$.  If the thread is migrated to a different core,
the instructions would be incoherent.

This depends on https://github.com/riscv/riscv-glibc/pull/22

Note this change does not cause ABI breakage, because previously we had
disallowed use of fs0-fs11 altogether in the soft-float ABI.

libgcc/ChangeLog

2017-11-04  Chih-Mao Chen <pkmx.tw@gmail.com>

	* config/riscv/div.S: Set symbol type to function.
	* config/riscv/muldi3.S: Likewise.
	* config/riscv/multi3.S: Likewise.

This supports reducing the stack alignment to 8 bytes for RV32I.

gcc/ChangeLog

2017-11-03  Andrew Waterman  <andrew@sifive.com>

        * config/riscv/riscv.opt (mpreferred-stack-boundary): New
        option.
        config/riscv/riscv.h (MIN_STACK_BUNDARY): New define.
        (ABI_STACK_BUNDARY): New define.
        (BIGGEST_ALIGNMENT): Respect the ABI stack boundary.
        (STACK_BOUNDARY): Likewise.
        (riscv_stack_boundary): New variable.
        config/riscv/riscv.c (riscv_stack_bundary): Likewise.
        (riscv_option_override): Handle -mpreferred-stack-boundary.

gcc/ChangeLog

2017-11-04  Andrew Waterman  <andrew@sifive.com>

        * config/riscv/riscv.c (TARGET_ASM_SELECT_SECTION): New define.
        (TARGET_HAVE_SRODATA_SECTION): New define.
        (riscv_select_section): New function.

It's not actually necessary to perform an explicit zero extension here
when we can roll it into the shift.  Since values in registers are
always kept sign extended we know the result of the high bits exactly.

gcc/ChangeLog

2017-11-04  Andrew Waterman  <andrew@sifive.com>

        * config/riscv/riscv.md (*lshrsi3_zero_extend): New pattern.

libgcc/ChangeLog

2017-11-04  Kito Cheng <kito.cheng@gmail.com>

       * config/riscv/t-elf: Use multi3.c instead of multi3.S.
       * config/riscv/multi3.c: New file.
       * config/riscv/multi3.S: Remove.

2017-08-02  Kito Cheng  <kito.cheng@gmail.com>

        * longlong.h [__riscv] (__umulsidi3): Define.
        [__riscv] (umul_ppmm) Likewise.
        [__riscv] (__muluw3) Likewise.

  - This build error was indroduced by "RISC-V: Implement movmemsi"
    and "RISC-V: Support -mpreferred-stack-boundary flag"

gcc/ChangeLog

2017-11-08  Kito Cheng  <kito.cheng@gmail.com>

        * config/riscv/riscv-protos.h (riscv_slow_unaligned_access_p):
        New extern.
        (MOVE_RATIO): Use riscv_slow_unaligned_access_p.
        config/riscv/riscv.c (predict.h): New include.
        (riscv_slow_unaligned_access_p): No longer static.
        (riscv_block_move_straight): Add require.
        config/riscv/riscv-protos.h (riscv_hard_regno_nregs): Delete.

git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@254554 138bc75d-0d04-0410-961f-82ee72b054a4

	PR fortran/82884
	* arith.c (gfc_hollerith2character): Clear pad.

2017-11-08  Steven G. Kargl  <kargl@gcc.gnu.org>

	PR fortran/82884
	* gfortran.dg/hollerith_character_array_constructor.f90: New test.


git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@254553 138bc75d-0d04-0410-961f-82ee72b054a4

	* config/i386/sse.md (<avx512>_eq<mode>3<mask_scalar_merge_name>,
	<avx512>_eq<mode>3<mask_scalar_merge_name>_1): Use
	nonimmediate_operand predicate for operand 1 instead of
	register_operand.


git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@254552 138bc75d-0d04-0410-961f-82ee72b054a4

On top of the previous vec_merge simplifications [1] we can add this pattern to perform
a store of a vec_concat of two 64-bit values in distinct registers as an STP.
This avoids constructing such a vector explicitly in a register and storing it as
a Q register.
This way for the code in the testcase we can generate:

construct_lane_1:
        ldp     d1, d0, [x0]
        fmov    d3, 1.0e+0
        fmov    d2, 2.0e+0
        fadd    d4, d1, d3
        fadd    d5, d0, d2
        stp     d4, d5, [x1, 32]
        ret

construct_lane_2:
        ldp     x2, x0, [x0]
        add     x3, x2, 1
        add     x4, x0, 2
        stp     x3, x4, [x1, 32]
        ret

instead of the current:
construct_lane_1:
        ldp     d0, d1, [x0]
        fmov    d3, 1.0e+0
        fmov    d2, 2.0e+0
        fadd    d0, d0, d3
        fadd    d1, d1, d2
        dup     v0.2d, v0.d[0]
        ins     v0.d[1], v1.d[0]
        str     q0, [x1, 32]
        ret

construct_lane_2:
        ldp     x2, x3, [x0]
        add     x0, x2, 1
        add     x2, x3, 2
        dup     v0.2d, x0
        ins     v0.d[1], x2
        str     q0, [x1, 32]
        ret

Bootstrapped and tested on aarch64-none-linux-gnu.

[1] https://gcc.gnu.org/ml/gcc-patches/2017-06/msg00272.html
    https://gcc.gnu.org/ml/gcc-patches/2017-06/msg00273.html
    https://gcc.gnu.org/ml/gcc-patches/2017-06/msg00274.html

	* config/aarch64/aarch64-simd.md (store_pair_lanes<mode>):
	New pattern.
	* config/aarch64/constraints.md (Uml): New constraint.
	* config/aarch64/predicates.md (aarch64_mem_pair_lanes_operand): New
	predicate.

	* gcc.target/aarch64/store_v2vec_lanes.c: New test.



git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@254551 138bc75d-0d04-0410-961f-82ee72b054a4

Another vec_merge simplification that's missing from simplify-rtx.c is transforming
a vec_merge of two vec_duplicates. For example:
(set (reg:V2DF 80)
    (vec_merge:V2DF (vec_duplicate:V2DF (reg:DF 84))
        (vec_duplicate:V2DF (reg:DF 81))
        (const_int 2)))

Can be transformed into the simpler:
(set (reg:V2DF 80)
    (vec_concat:V2DF (reg:DF 81)
                (reg:DF 84)))

I believe this should always be beneficial.
I'm still looking into finding a small testcase demonstrating this, but on aarch64 SPEC
I've seen this eliminate some really bizzare codegen where GCC was generating nonsense like:
  ldr q18, [sp, 448]
  ins v18.d[0], v23.d[0]
  ins v18.d[1], v22.d[0]

With q18 being pushed and popped off the stack in the prologue and epilogue of the function!
These are large files from SPEC that I haven't been able to analyse yet as to why GCC even attempts
to do that, but with this patch it doesn't try to load a register and overwrite all its lanes.
This patch shaves off about 5k of code size from zeusmp on aarch64 at -O3, so I believe it's a good
thing to do. 

	* simplify-rtx.c (simplify_ternary_operation): Simplify vec_merge
	of two vec_duplicates into a vec_concat.


git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@254550 138bc75d-0d04-0410-961f-82ee72b054a4

Another vec_merge simplification that's missing is transforming:
(vec_merge (vec_duplicate x) (vec_concat (y) (z)) (const_int N))
into
(vec_concat x z) if N == 1 (0b01) or
(vec_concat y x) if N == 2 (0b10)

For the testcase in this patch on aarch64 this allows us to try matching during combine the pattern:
(set (reg:V2DI 78 [ x ])
    (vec_concat:V2DI
        (mem:DI (reg/v/f:DI 76 [ y ]) [1 *y_4(D)+0 S8 A64])
        (mem:DI (plus:DI (reg/v/f:DI 76 [ y ])
                (const_int 8 [0x8])) [1 MEM[(long long int *)y_4(D) + 8B]+0 S8 A64])))

rather than the more complex:
(set (reg:V2DI 78 [ x ])
    (vec_merge:V2DI (vec_duplicate:V2DI (mem:DI (plus:DI (reg/v/f:DI 76 [ y ])
                    (const_int 8 [0x8])) [1 MEM[(long long int *)y_4(D) + 8B]+0 S8 A64]))
        (vec_duplicate:V2DI (mem:DI (reg/v/f:DI 76 [ y ]) [1 *y_4(D)+0 S8 A64]))
        (const_int 2 [0x2])))

We don't actually have an aarch64 pattern for the simplified version above, but it's a simple enough
form to add, so this patch adds such a pattern that performs a concatenated load of two 64-bit vectors
in adjacent memory locations as a single Q-register LDR. The new aarch64 pattern is needed to demonstrate
the effectiveness of the simplify-rtx change, so I've kept them together as one patch.

Now for the testcase in the patch we can generate:
construct_lanedi:
        ldr     q0, [x0]
        ret

construct_lanedf:
        ldr     q0, [x0]
        ret

instead of:
construct_lanedi:
        ld1r    {v0.2d}, [x0]
        ldr     x0, [x0, 8]
        ins     v0.d[1], x0
        ret

construct_lanedf:
        ld1r    {v0.2d}, [x0]
        ldr     d1, [x0, 8]
        ins     v0.d[1], v1.d[0]
        ret

The new memory constraint Utq is needed because we need to allow only the Q-register addressing modes but
the MEM expressions in the RTL pattern have 64-bit vector modes, and if we don't constrain them they will
allow the D-register addressing modes during register allocation/address mode selection, which will produce
invalid assembly.

Bootstrapped and tested on aarch64-none-linux-gnu. 

	* simplify-rtx.c (simplify_ternary_operation, VEC_MERGE):
	Simplify vec_merge of vec_duplicate and vec_concat.
	* config/aarch64/constraints.md (Utq): New constraint.
	* config/aarch64/aarch64-simd.md (load_pair_lanes<mode>): New
	define_insn.

	* gcc.target/aarch64/load_v2vec_lanes_1.c: New test.



git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@254549 138bc75d-0d04-0410-961f-82ee72b054a4

I'm trying to improve some of the RTL-level handling of vector lane operations on aarch64 and that
involves dealing with a lot of vec_merge operations. One simplification that I noticed missing
from simplify-rtx are combinations of vec_merge with vec_duplicate.
In this particular case:
(vec_merge (vec_duplicate (X)) (const_vector [A, B]) (const_int N))

which can be replaced with

(vec_concat (X) (B)) if N == 1 (0b01) or
(vec_concat (A) (X)) if N == 2 (0b10).

For the aarch64 testcase in this patch this simplifications allows us to try to combine:
(set (reg:V2DI 77 [ x ])
    (vec_concat:V2DI (mem:DI (reg:DI 0 x0 [ y ]) [1 *y_3(D)+0 S8 A64])
        (const_int 0 [0])))

instead of the more complex:
(set (reg:V2DI 77 [ x ])
    (vec_merge:V2DI (vec_duplicate:V2DI (mem:DI (reg:DI 0 x0 [ y ]) [1 *y_3(D)+0 S8 A64]))
        (const_vector:V2DI [
                (const_int 0 [0])
                (const_int 0 [0])
            ])
        (const_int 1 [0x1])))


For the simplified form above we already have an aarch64 pattern: *aarch64_combinez<mode> which
is missing a DI/DFmode version due to an oversight, so this patch extends that pattern as well to
use the VDC mode iterator that includes DI and DFmode (as well as V2HF which VD_BHSI was missing).
The aarch64 hunk is needed to see the benefit of the simplify-rtx.c hunk, so I didn't split them
into separate patches.

Before this for the testcase we'd generate:
construct_lanedi:
        movi    v0.4s, 0
        ldr     x0, [x0]
        ins     v0.d[0], x0
        ret

construct_lanedf:
        movi    v0.2d, 0
        ldr     d1, [x0]
        ins     v0.d[0], v1.d[0]
        ret

but now we can generate:
construct_lanedi:
        ldr     d0, [x0]
        ret

construct_lanedf:
        ldr     d0, [x0]
        ret

Bootstrapped and tested on aarch64-none-linux-gnu.


	* simplify-rtx.c (simplify_ternary_operation, VEC_MERGE):
	Simplify vec_merge of vec_duplicate and const_vector.
	* config/aarch64/predicates.md (aarch64_simd_or_scalar_imm_zero):
	New predicate.
	* config/aarch64/aarch64-simd.md (*aarch64_combinez<mode>): Use VDC
	mode iterator.  Update predicate on operand 1 to
	handle non-const_vec constants.  Delete constraints.
	(*aarch64_combinez_be<mode>): Likewise for operand 2.

	* gcc.target/aarch64/construct_lane_zero_1.c: New test.



git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@254548 138bc75d-0d04-0410-961f-82ee72b054a4

	* lib-xref.ads, lib-xref-spark_specific.adb
	(Traverse_Compilation_Unit): Move declaration to package body.

2017-11-08  Hristian Kirtchev  <kirtchev@adacore.com>

	* exp_spark.adb (Expand_SPARK_N_Object_Renaming_Declaration): Obtain
	the type of the renaming from its defining entity, rather then the
	subtype mark as there may not be a subtype mark.

2017-11-08  Jerome Lambourg  <lambourg@adacore.com>

	* adaint.c, s-oscons-tmplt.c, init.c, libgnat/system-qnx-aarch64.ads,
	libgnarl/a-intnam__qnx.ads, libgnarl/s-intman__qnx.adb,
	libgnarl/s-osinte__qnx.ads, libgnarl/s-qnx.ads,
	libgnarl/s-taprop__qnx.adb, s-oscons-tmplt.c, sigtramp-qnx.c,
	terminals.c: Initial port of GNAT for aarch64-qnx

2017-11-08  Elisa Barboni  <barboni@adacore.com>

	* exp_util.adb (Find_DIC_Type): Move...
	* sem_util.ads, sem_util.adb (Find_DIC_Type): ... here.

2017-11-08  Justin Squirek  <squirek@adacore.com>

	* sem_res.adb (Resolve_Allocator): Add info messages corresponding to
	the owner and corresponding coextension.

2017-11-08  Ed Schonberg  <schonberg@adacore.com>

	* sem_aggr.adb (Resolve_Delta_Aggregate): Divide into the
	following separate procedures.
	(Resolve_Delta_Array_Aggregate): Previous code form
	Resolve_Delta_Aggregate.
	(Resolve_Delta_Record_Aggregate): Extend previous code to cover latest
	ARG decisions on the legality rules for delta aggregates for records:
	in the case of a variant record, components from different variants
	cannot be specified in the delta aggregate, and this must be checked
	statically.



git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@254547 138bc75d-0d04-0410-961f-82ee72b054a4

	* spark_xrefs.ads (SPARK_Scope_Record): Remove File_Num component.
	* lib-xref-spark_specific.adb (Add_SPARK_Scope): Skip initialization of
	removed component.

2017-11-08  Gary Dismukes  <dismukes@adacore.com>

	* sem_ch4.adb: Minor typo fix.


git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@254546 138bc75d-0d04-0410-961f-82ee72b054a4

	* spark_xrefs.ads (SPARK_Scope_Record): Remove Spec_File_Num and
	Spec_Scope_Num components.
	* spark_xrefs.adb (dspark): Skip pretty-printing to removed components.
	* lib-xref-spark_specific.adb (Add_SPARK_Scope): Skip initialization of
	removed components.
	(Collect_SPARK_Xrefs): Skip setting proper values of removed
	components.

2017-11-08  Gary Dismukes  <dismukes@adacore.com>

	* exp_ch4.adb (Expand_N_Type_Conversion): Add test that the selector
	name is a discriminant in check for unconditional accessibility
	violation within instances.


git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@254545 138bc75d-0d04-0410-961f-82ee72b054a4

2017-11-08  Piotr Trojanek  <trojanek@adacore.com>

	* lib-xref-spark_specific.adb (Add_SPARK_Xrefs): Remove special-case
	for constants (with variable input).
	(Is_Constant_Object_Without_Variable_Input): Remove.

2017-11-08  Hristian Kirtchev  <kirtchev@adacore.com>

	* exp_ch9.adb, sem_disp.adb, sem_util.adb: Minor reformatting.

2017-11-08  Piotr Trojanek  <trojanek@adacore.com>

	* spark_xrefs.ads (Rtype): Remove special-casing of constants for SPARK
	cross-references.
	(dspark): Remove hardcoded table bound.

2017-11-08  Ed Schonberg  <schonberg@adacore.com>

	* sem_ch4.adb (Analyze_Aggregate): For Ada2020 delta aggregates, use
	the type of the base of the construct to determine the type (or
	candidate interpretations) of the delta aggregate. This allows the
	construct to appear in a context that expects a private extension.
	* sem_res.adb (Resolve): Handle properly a delta aggregate with an
	overloaded base.

gcc/testsuite/

2017-11-08  Ed Schonberg  <schonberg@adacore.com>

	* gnat.dg/delta_aggr.adb: New testcase.


git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@254544 138bc75d-0d04-0410-961f-82ee72b054a4

	* spark_xrefs.ads (SPARK_Xref_Record): Replace file and scope indices
	with Entity_Id of the reference.
	* spark_xrefs.adb (dspark): Adapt pretty-printing routine.
	* lib-xref-spark_specific.adb (Add_SPARK_Xrefs): Store Entity_Id of the
	reference, not the file and scope indices.

2017-11-08  Arnaud Charlet  <charlet@adacore.com>

	* errout.ads (Current_Node): New.
	* errout.adb (Error_Msg): Use Current_Node.
	* par-ch6.adb, par-ch7.adb, par-ch9.adb, par-util.adb: Set Current_Node
	when relevant.
	* style.adb: Call Error_Msg_N when possible.


git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@254543 138bc75d-0d04-0410-961f-82ee72b054a4

	* spark_xrefs.ads (SPARK_Scope_Record): Rename Scope_Id component to
	Entity.
	* lib-xref-spark_specific.adb, spark_xrefs.adb: Propagate renaming of
	the Scope_Id record component.


git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@254542 138bc75d-0d04-0410-961f-82ee72b054a4

	* spark_xrefs.ads (SPARK_File_Record): Remove string components.
	* spark_xrefs.adb (dspark): Remove pretty-printing of removed
	SPARK_File_Record components.
	* lib-xref-spark_specific.adb (Add_SPARK_File): Do not store string
	representation of files/units.


git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@254541 138bc75d-0d04-0410-961f-82ee72b054a4

	* lib-xref.ads, lib-xref-spark_specific.adb (Traverse_Declarations):
	Remove Inside_Stubs parameter.



git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@254540 138bc75d-0d04-0410-961f-82ee72b054a4

	* spark_xrefs.ads (SPARK_Xref_Record): Referenced object is now
	represented by Entity_Id.
	(SPARK_Scope_Record): Referenced scope (e.g. subprogram) is now
	represented by Entity_Id; this information is not repeated as
	Scope_Entity.
	(Heap): Moved from lib-xref-spark_specific.adb, to reside next to
	Name_Of_Heap_Variable.
	* spark_xrefs.adb (dspark): Adapt debug routine to above changes in
	data types.
	* lib-xref-spark_specific.adb: Adapt routines for populating SPARK
	scope and xrefs tables to above changes in data types.

2017-11-08  Justin Squirek  <squirek@adacore.com>

	* sem_ch8.adb (Mark_Use_Clauses): Add condition to always mark the
	primitives of generic actuals.
	(Mark_Use_Type): Add recursive call to properly mark class-wide type's
	base type clauses as per ARM 8.4 (8.2/3).

2017-11-08  Ed Schonberg  <schonberg@adacore.com>

	* sem_ch6.adb (Analyze_Generic_Subprobram_Body): Validate
	categorization dependency of the body, as is done for non-generic
	units.
	(New_Overloaded_Entity, Visible_Part_Type): Remove linear search
	through declarations (Simple optimization, no behavior change).



git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@254539 138bc75d-0d04-0410-961f-82ee72b054a4

	* spark_xrefs.ads (SPARK_Xref_Record): Remove inessential components.
	(SPARK_Scope_Record): Remove inessential components.
	* spark_xrefs.adb (dspark): Remove pretty-printing of removed record
	components.
	* lib-xref-spark_specific.adb (Add_SPARK_Scope): Remove setting of
	removed record components.
	(Add_SPARK_Xrefs): Remove setting of removed record components.



git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@254538 138bc75d-0d04-0410-961f-82ee72b054a4

	a value.


git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@254537 138bc75d-0d04-0410-961f-82ee72b054a4

	* gimple-ssa-store-merging.c (struct store_operand_info): Add bit_not_p
	data member.
	(store_operand_info::store_operand_info): Initialize it to false.
	(pass_store_merging::terminate_all_aliasing_chains): Rewritten to use
	ref_maybe_used_by_stmt_p and stmt_may_clobber_ref_p on lhs of each
	store in the group, and if chain_info is non-NULL, to ignore altogether
	that chain.
	(compatible_load_p): Fail if bit_not_p does not match.
	(imm_store_chain_info::output_merged_store): Handle bit_not_p loads.
	(handled_load): Fill in bit_not_p.  Handle BIT_NOT_EXPR.
	(pass_store_merging::process_store): Adjust
	terminate_all_aliasing_chains calls to pass NULL in all current spots,
	call terminate_all_aliasing_chains newly when adding a store into
	a chain with non-NULL chain_info.

	* gcc.dg/store_merging_2.c: Expect 3 store mergings instead of 2.
	* gcc.dg/store_merging_13.c (f7, f8, f9, f10, f11, f12, f13): New
	functions.
	(main): Test also those.  Expect 13 store mergings instead of 6.
	* gcc.dg/store_merging_14.c (f7, f8, f9): New functions.
	(main): Test also those.  Expect 9 store mergings instead of 6.


git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@254536 138bc75d-0d04-0410-961f-82ee72b054a4

	* lib-xref-spark_specific.adb (Add_SPARK_Xrefs): Remove dead check for
	empty entities.



git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@254535 138bc75d-0d04-0410-961f-82ee72b054a4

Simplify aarch64_can_eliminate - if we need a frame pointer, we must
eliminate to HARD_FRAME_POINTER_REGNUM.  Rather than hardcoding all
combinations from the ELIMINABLE_REGS list, just do the correct check.

    gcc/
	* config/aarch64/aarch64.c (aarch64_can_eliminate): Simplify logic.


git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@254534 138bc75d-0d04-0410-961f-82ee72b054a4

To implement -fomit-leaf-frame-pointer, there are 2 places where we need
to check whether we have to use a frame chain (since register allocation
may allocate LR in a leaf function that omits the frame pointer, but if
LR is spilled we must emit a frame chain).  To simplify this do not force
frame_pointer_needed via aarch64_frame_pointer_required, but enable the
frame chain in aarch64_layout_frame.  Now aarch64_frame_pointer_required
can be removed and aarch64_can_eliminate is simplified.

    gcc/
	* config/aarch64/aarch64.c (aarch64_frame_pointer_required)
	Remove.
	(aarch64_layout_frame): Initialise emit_frame_chain.
	(aarch64_can_eliminate): Remove omit leaf frame pointer code.
	(TARGET_FRAME_POINTER_REQUIRED): Remove define.

    testsuite/
	* gcc.target/aarch64/dwarf-cfa-reg.c: Update.


git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@254533 138bc75d-0d04-0410-961f-82ee72b054a4

2017-11-08  Javier Miranda  <miranda@adacore.com>

	* sem_disp.adb (Is_Inherited_Public_Operation): Extend the
	functionality of this routine to handle multiple levels of derivations.

2017-11-08  Hristian Kirtchev  <kirtchev@adacore.com>

	* einfo.adb: Elist36 is now used as Nested_Scenarios.
	(Nested_Scenarios): New routine.
	(Set_Nested_Scenarios): New routine.
	(Write_Field36_Name): New routine.
	* einfo.ads: Add new attribute Nested_Scenarios along with occurrences
	in entities.
	(Nested_Scenarios): New routine along with pragma Inline.
	(Set_Nested_Scenarios): New routine along with pragma Inline.
	* sem_elab.adb (Find_And_Process_Nested_Scenarios): New routine.
	(Process_Nested_Scenarios): New routine.
	(Traverse_Body): When a subprogram body is traversed for the first
	time, find, save, and process all suitable scenarios found within.
	Subsequent traversals of the same subprogram body utilize the saved
	scenarios.

2017-11-08  Piotr Trojanek  <trojanek@adacore.com>

	* lib-xref-spark_specific.adb (Add_SPARK_Scope): Remove detection of
	protected operations.
	(Add_SPARK_Xrefs): Simplify detection of empty entities.
	* get_spark_xrefs.ads, get_spark_xrefs.adb, put_spark_xrefs.ads,
	put_spark_xrefs.adb, spark_xrefs_test.adb: Remove code for writing,
	reading and testing SPARK cross-references stored in the ALI files.
	* lib-xref.ads (Output_SPARK_Xrefs): Remove.
	* lib-writ.adb (Write_ALI): Do not write SPARK cross-references to the
	ALI file.
	* spark_xrefs.ads, spark_xrefs.adb (pspark): Remove, together
	with description of the SPARK xrefs ALI format.
	* gcc-interface/Make-lang.in (GNAT_ADA_OBJS): Remove get_spark_refs.o
	and put_spark_refs.o.

2017-11-08  Hristian Kirtchev  <kirtchev@adacore.com>

	* exp_ch4.adb (Apply_Accessibility_Check): Do not finalize the object
	when the associated access type is subject to pragma
	No_Heap_Finalization.
	* exp_intr.adb (Expand_Unc_Deallocation): Use the available view of the
	designated type in case it comes from a limited withed unit.

gcc/testsuite/

2017-11-08  Javier Miranda  <miranda@adacore.com>

	* gnat.dg/overriding_ops2.adb, gnat.dg/overriding_ops2.ads,
	gnat.dg/overriding_ops2_pkg.ads, gnat.dg/overriding_ops2_pkg-high.ads:
	New testcase.





git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@254532 138bc75d-0d04-0410-961f-82ee72b054a4

	* exp_ch3.adb (Expand_N_Object_Declaration): Save and restore relevant
	SPARK-related flags.  Add ??? comment.
	* exp_util.adb (Insert_Actions): Add an entry for node
	N_Variable_Reference_Marker.
	* sem.adb (Analyze): Add an entry for node N_Variable_Reference_Marker.
	* sem_ch8.adb (Find_Direct_Name): Add constant Is_Assignment_LHS. Build
	and record a variable reference marker for the current name.
	(Find_Expanded_Name): Add constant Is_Assignment_LHS. Build and record
	a variable reference marker for the current name.
	* sem_elab.adb (Build_Variable_Reference_Marker): New routine.
	(Extract_Variable_Reference_Attributes): Reimplemented.
	(Info_Scenario): Add output for variable references and remove output
	for variable reads.
	(Info_Variable_Read): Removed.
	(Info_Variable_Reference): New routine.
	(Is_Suitable_Scenario): Variable references are now suitable scenarios
	while variable reads are not.
	(Output_Active_Scenarios): Add output for variable references and
	remove output for variable reads.
	(Output_Variable_Read): Removed.
	(Output_Variable_Reference): New routine.
	(Process_Variable_Read): Removed.
	(Process_Variable_Reference): New routine.
	(Process_Variable_Reference_Read): New routine.
	* sem_elab.ads (Build_Variable_Reference_Marker): New routine.
	* sem_res.adb (Resolve_Actuals): Build and record a variable reference
	marker for the current actual.
	* sem_spark.adb (Check_Node): Add an entry for node
	N_Variable_Reference_Marker.
	* sem_util.adb (Within_Subprogram_Call): Moved to the library level.
	* sem_util.ads (Within_Subprogram_Call): Moved to the library level.
	* sinfo.adb (Is_Read): New routine.
	(Is_Write): New routine.
	(Target): Updated to handle variable reference markers.
	(Set_Is_Read): New routine.
	(Set_Is_Write): New routine.
	(Set_Target): Updated to handle variable reference markers.
	* sinfo.ads: Add new attributes Is_Read and Is_Write along with
	occurrences in nodes. Update attribute Target. Add new node
	kind N_Variable_Reference_Marker.
	(Is_Read): New routine along with pragma Inline.
	(Is_Write): New routine along with pragma Inline.
	(Set_Is_Read): New routine along with pragma Inline.
	(Set_Is_Write): New routine along with pragma Inline.
	* sprint.adb (Sprint_Node_Actual): Add an entry for node
	N_Variable_Reference_Marker.



git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@254531 138bc75d-0d04-0410-961f-82ee72b054a4