Skip to content
GitLab
  1. Feb 16, 2018
  3. Nov 08, 2017
    • palmer's avatar
      RISC-V: Implement movmemsi · b7311497
      palmer authored 
      Without this we aren't getting proper memcpy inlining on RISC-V systems,
which is particularly disastrous for Dhrystone performance on RV32IM
systems.

gcc/ChangeLog

2017-11-07  Andrew Waterman  <andrew@sifive.com>

        * config/riscv/riscv-protos.h (riscv_hard_regno_nregs): New
        prototype.
        (riscv_expand_block_move): Likewise.
        gcc/config/riscv/riscv.h (MOVE_RATIO): Tune cost to movmemsi
        implementation.
        (RISCV_MAX_MOVE_BYTES_PER_LOOP_ITER): New define.
        (RISCV_MAX_MOVE_BYTES_STRAIGHT): New define.
        gcc/config/riscv/riscv.c (riscv_block_move_straight): New
        function.
        (riscv_adjust_block_mem): Likewise.
        (riscv_block_move_loop): Likewise.
        (riscv_expand_block_move): Likewise.
        gcc/config/riscv/riscv.md (movmemsi): New pattern.

git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@254501 138bc75d-0d04-0410-961f-82ee72b054a4
      b7311497
    • palmer's avatar
      RISC-V: Define MUSL_DYNAMIC_LINKER · 605bc7b5
      palmer authored 
      Use no suffix at all in the musl dynamic linker name for hard
float ABI. Use -sf and -sp suffixes in musl dynamic linker name
for soft float and single precision ABIs. The following table
outlines the musl interpreter names for the RISC-V ABI names.

musl interpreter        | RISC-V ABI
----------------------- | -------------
ld-musl-riscv32.so.1    | riscv32-ilp32d
ld-musl-riscv64.so.1    | riscv64-lp64d
ld-musl-riscv32-sf.so.1 | riscv32-ilp32
ld-musl-riscv64-sf.so.1 | riscv64-lp64
ld-musl-riscv32-sp.so.1 | riscv32-ilp32f
ld-musl-riscv64-sp.so.1 | riscv64-lp64f

gcc/ChangeLog

2017-11-06  Michael Clark  <michaeljclark@mac.com>

        * config/riscv/linux.h (MUSL_ABI_SUFFIX): New define.
        (MUSL_DYNAMIC_LINKER): Likewise.

git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@254500 138bc75d-0d04-0410-961f-82ee72b054a4
      605bc7b5
  5. Nov 05, 2017
    • palmer's avatar
      RISC-V: Emit "i" suffix for instructions with immediate operands · 2423096b
      palmer authored 
      This changes makes GCC asm output use instruction names that are
consistent with the RISC-V ISA manual.  The assembler accepts
immediate-operand instructions without the "i" suffix, so this all
worked before, it's just a bit cleaner to match the ISA manual more
closely.

gcc/ChangeLog

2017-10-03  Michael Clark  <michaeljclark@mac.com>

        * config/riscv/riscv.c (riscv_print_operand): Add a 'i' format.
        config/riscv/riscv.md (addsi3): Use 'i' for immediates.
        (adddi3): Likewise.
        (*addsi3_extended): Likewise.
        (*addsi3_extended2): Likewise.
        (<optab>si3): Likewise.
        (<optab>di3): Likewise.
        (<optab><mode>3): Likewise.
        (<*optabe>si3_internal): Likewise.
        (zero_extendqi<SUPERQI:mode>2): Likewise.
        (*add<mode>hi3): Likewise.
        (*xor<mode>hi3): Likewise.
        (<optab>di3): Likewise.
        (*<optab>si3_extend): Likewise.
        (*sge<u>_<X:mode><GPR:mode>): Likewise.
        (*slt<u>_<X:mode><GPR:mode>): Likewise.
        (*sle<u>_<X:mode><GPR:mode>): Likewise.

git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@254418 138bc75d-0d04-0410-961f-82ee72b054a4
      2423096b
    • palmer's avatar
      RISC-V: If -m[no-]strict-align is not passed, assume its value from -mtune · 327d99b0
      palmer authored 
      2017-11-04  Andrew Waterman  <andrew@sifive.com>

	* config/riscv/riscv.c (riscv_option_override): Conditionally set
	TARGET_STRICT_ALIGN based upon -mtune argument.

git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@254417 138bc75d-0d04-0410-961f-82ee72b054a4
      327d99b0
    • palmer's avatar
      RISC-V: Set SLOW_BYTE_ACCESS=1 · f34a83e8
      palmer authored 
      When implementing the RISC-V port, I took the name of this macro at
face value.  It appears we were mistaken in what this means, here's a
quote from the SPARC port that better describes what SLOW_BYTE_ACCESS
does

    /* Nonzero if access to memory by bytes is slow and undesirable.
       For RISC chips, it means that access to memory by bytes is no
       better than access by words when possible, so grab a whole word
       and maybe make use of that.  */

I've added the comment to our port as well.

See https://gcc.gnu.org/ml/gcc/2017-08/msg00202.html for more
discussion.  Thanks to Michael Clark and Andrew Pinski for the help!

gcc/ChangeLog

2017-11-04  Andrew Waterman  <andrew@sifive.com>

        * config/riscv/riscv.h (SLOW_BYTE_ACCESS): Change to 1.

git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@254416 138bc75d-0d04-0410-961f-82ee72b054a4
      f34a83e8
  7. Nov 03, 2017
  9. Nov 02, 2017
  11. Oct 27, 2017
  13. Oct 26, 2017
    • palmer's avatar
      RISC-V: Add Sign/Zero extend patterns for PIC loads · d13dd024
      palmer authored 
      Loads on RISC-V are sign-extending by default, but we weren't telling
GCC this in our PIC load patterns.  This corrects the problem, and adds
a zero-extending pattern as well.

gcc/ChangeLog

2017-10-25  Palmer Dabbelt  <palmer@dabbelt.com>

       * config/riscv/riscv.md (ZERO_EXTEND_LOAD): Define.
       * config/riscv/pic.md (local_pic_load): Rename to local_pic_load_s,
       mark as a sign-extending load.
       (local_pic_load_u): Define.

git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@254092 138bc75d-0d04-0410-961f-82ee72b054a4
      d13dd024
  15. Aug 25, 2017
    • palmer's avatar
      RISC-V: Add -mstrict-align option · 34137563
      palmer authored 
      The RISC-V user ISA permits misaligned accesses, but they may trap
and be emulated.  That emulation software needs to be compiled assuming
strict alignment.

Even when strict alignment is not required, set SLOW_UNALIGNED_ACCESS
based upon -mtune to avoid a performance pitfall.

gcc/ChangeLog:

2017-05-04  Andrew Waterman  <andrew@sifive.com>

	* config/riscv/riscv.opt (mstrict-align): New option.
	* config/riscv/riscv.h (STRICT_ALIGNMENT): Use it.  Update comment.
	(SLOW_UNALIGNED_ACCESS): Define.
	(riscv_slow_unaligned_access): Declare.
	* config/riscv/riscv.c (riscv_tune_info): Add slow_unaligned_access
	field.
	(riscv_slow_unaligned_access): New variable.
	(rocket_tune_info): Set slow_unaligned_access to true.
	(optimize_size_tune_info): Set slow_unaligned_access to false.
	(riscv_cpu_info_table): Add entry for optimize_size_tune_info.
	(riscv_valid_lo_sum_p): Use TARGET_STRICT_ALIGN.
	(riscv_option_override): Set riscv_slow_unaligned_access.
        * doc/invoke.texi: Add -mstrict-align to RISC-V.

git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@247659 138bc75d-0d04-0410-961f-82ee72b054a4
      34137563
    • palmer's avatar
      RISC-V: Unify indention in riscv.md · f47f9c2b
      palmer authored 
      This contains only whitespace changes.

gcc/ChangeLog

2017-05-04  Kito Cheng  <kito.cheng@gmail.com>

	* config/riscv/riscv.md: Unify indentation.

git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@247658 138bc75d-0d04-0410-961f-82ee72b054a4
      f47f9c2b
  17. Aug 14, 2017
  19. Aug 13, 2017
  21. Aug 12, 2017
  23. Aug 11, 2017
  25. Aug 10, 2017
  27. Aug 09, 2017
  29. Aug 08, 2017
  31. Aug 07, 2017
  33. Aug 06, 2017
  35. Aug 05, 2017
  37. Aug 04, 2017
  39. Aug 03, 2017
  41. Aug 02, 2017