and fix bugs

  2.optimize auto-vectorization of conditional operations

* PR for RVV support using splitted small chunks

* add zfh string support for -march:
  user can use -march=rv64gcv_zfh to enable zfh support

* add RVV vector mode including full vector mode, partial vector mode
  full tuple mode, partial tuple mode

* add rvv instruction type. It is used for instruction scheduling

* add zfh support in riscv.md

* add strlen and strcmp and memcpy support using rvv instructions

* add soft half-precision float

* add predicated and constraint for RVV

* add RVV vector registers

* add header "riscv_vector.h" for RVV

* add poly_int movement support:
  For example: (set DI reg) (const_poly_int 16 16).
  This pattern is translated into asm csrr reg, vlenb.
  For other poly_int value, we translate it into
  csrr reg, vlenb + scalar operation (shift, mul, plus).

* stack manipulation && prologue handling && epilogue handling

* add implementation for memcpy, strlen, strcpy and strcmp

* add python to generates iterators.def:
  riscv_md_parser.py this script is used to generate riscv-vector-builtins-iterators.def
  file using vector-iterators.md.
  The definition of riscv-vector-builtins-iterators.def is used by intrinsic definition
  For example:If we define DEF_RVV_FUNCTION(vsetvl, config, (1, VITER(VI, signed))....)
  the vsetvl of all machine_mode in the "VI" iterators are added into the builtins.

* add vector_type and tuple_type definition using macro DEF_RVV_TYPE
  For example: DEF_RVV_TYPE (float16, fp16_type_node). This macro will
  define all data_type (vfloat16m1_t .....)
  and tuple type (vfloat16m1x2_t ......)

* add RVV intrinsic framework and add RVV Configuration-Setting and Utility Functions
  which are defined as misc(The name can be changed) functions.For example:
  1.readvl. 2.vreinterpret 3.vlmul_ext 4.vlmul_trunc 5.vundefined
  6.vset 7.vget

* add vlm, vsm, vle, vse intrinsics

* add strided load store intrinsic (vlse and vsse)

* add indexed load store (vluxei vsuxei vloxei vluxei)

* add vleff load. This intrinsic is special we use gimple fold for
  the intrinsic.

* add segment load store and finish all load store implementation

* add load store MD patterns for last patterns(Forgot add it in the
  last commit).

* add integer arithmetic intrinsics(vadd,vsub,vrsub,vwadd,vwsub,
  vext,vzext,vadc,vsbc,vmadc,vmsbc,vand,vor,vxor,vsll,vsrl,vsra,
  vmscmp,vmin,vmax,vmul,vmulh,vwmul,vdiv,vrem,vmadd,vnmsac,vmacc,
  vnmsub,vwmacc,vmerge,vmv

* add chapter 12. fixed-point arithmetic intrinsics

* add chapter 13. fixed-point arithmetic arithmetic

* add chapter 14. vector reduction intrinsics

* add chapter 15 vector mask intrinsics

* add chapter 16. permutation intrinsics

* add RVV intrinsic framework to riscv-builtins.cc:
  we seperate builtins into 2 types:
  1. RISCV_BUILTIN_VECTOR (RVV intrinsic)
  2. RISCV_BUILTIN_GENERAL(Normal intrinsic that original RISCV support)

* add insert-vsetvli PASS. This is used for insert vsetvli instruction
  for every RVV instructions. The algorithm is following the LLVM

* add #pragma riscv intrinsic "vector" support for RVV intrinsics

* change all HOST_WIDE_INT into poly_int64. Because we should use
  poly_int for scalable vector

* add zfh support in riscv.cc

* add csrr %0,vlenb asm support for RVV

* add RVV vector function arg support:
  we follows the LLVM: v0 is used to pass mask register.
  v8 - v23 are used to pass vector register

* add mriscv-vector-bits compile option analysis

* add mangle and floating-point target hook

* add scalable vector configuration target hook

* add autovectorization target hook support and
  autovectorization patterns :vec_duplicate

* add vector alignment target hook

* add vector initialization auto-vectorization patterns:
  vec_set vec_insert vec_init vec_extract...
  The vec_init pattern is quite complicated, the implementation is
  in the riscv.cc (riscv_vector_expand_vector_init)

* add load_lanes && store lanes && gather_load && scatter_store
  (no mask) auto-vectorization patterns

* add mask target hook support
  add mask load store auto-vectorization support

* add auto-vectorizaiton patterns:unary operation

* add auto-vectorization patterns:conversion

* add auto-vectorizaiton patterns:binary operation

* add auto-vectorization patterns:ternary operation

* add auto-vectorization patterns:reduction operation

* add sew=64 support vx support in RV32 system.

* add vcond vec_cmp vcond_mask auto-vectorization patterns support

* add INT->FP conversion and FP->INT conversion auto-vectorization support

* add auto-vectorization support: while_len. This is a special
  pattern for RVV loop handling

* add while_len support (including MD patterns)

* add len_ load/store auto-vectorization support (including continues
  load store, gather/scatter, array load/store)(with mask or without
  mask)

* add auto-vectorization vector permute support

* add len_operation (add,sub,....) and len_shift auto-vectorization
  support

* add len_conversion auto-vectorization support

* add len comparision and len_vcond auto-vectorization support

* add mixed operations

* add vector-scalar mixed operation auto-vectorization support

* add new target hook doc

* add FMA missing information

* add poly_uint_for_modes support.
  According to RVV spec, the maximum vector length is 65536 which
  will overflow in poly_int16, so we add poly_uint_for_modes support
  to support 65536 vector length

* add COST model files (unfinished)

* add rvv testcase including intrinsic+auto-vectorization

* fix bugs of tree-vect-stmts.cc

* fix issues of riscv.h

* fix indent issues

* remove useless comments and vsat vxrm

* fix cpymem strlen movstr cmpstr

* fix whitespace and code stype

* fix whitespace

* collect format and indent issues and fix them

* remove redundant target hook definition

* add no trapping floating-point comparision support

* fix bugs

* refine intrinsic definition macro

* add nontuple segment load store support and testcase

* merge and rename the testcase so that the test files are
  manageable and files are reduced.

* add reduction auto-vectorization tests
  and fix bugs of reduction auto-vectorization

* refine load store testcase

* add widen reduction optimization and testcase

* remove redundant cond_* vs patterns

* reconstitute the RVV functions framework: Move all the RVV releted
  functions from riscv.cc into riscv-vector.cc.

* fix riscv-insert-vsetvli.cc issues

* rewrite RVV machine description files
  vector.md (base RVV)
  vector-auto.md (auto-vectorization)
  vector-opt.md (optimization)

* rewrite the vcond auto-vectorization

* remove redundant constraint

This reverts commit 3604e5b7.

* Support RVV Features including intrinsic and auto-vectorization
  Enable RVV intrinsic support:
   Users can use #pragma riscv intrinsic "vector"
   or #include <riscv_vector.h>
  Enable auto-vectorization support:
   use -mrvv compile option.
  Enable VLS auto-vectorization support:
   use -mrvv -mriscv-vector-bits=128/.../65536

* delete loadstore tests because it has too many files
  we will refine the tests and add them later.
  add len_* vcond_mask_vs and len_* vcond_mask_sv support

* delete the rvv tests

* add rvv testcases

* delete rvv testcase again

* add rvv testcase for the next update

* Revert "Daily bump."

This reverts commit 0d31c8ec.

* Support RVV Features including intrinsic and auto-vectorization
  Enable RVV intrinsic support:
   Users can use #pragma riscv intrinsic "vector"
   or #include <riscv_vector.h>
  Enable auto-vectorization support:
   use -mrvv compile option.
  Enable VLS auto-vectorization support:
   use -mrvv -mriscv-vector-bits=128/.../65536

* delete loadstore tests because it has too many files
  we will refine the tests and add them later.
  add len_* vcond_mask_vs and len_* vcond_mask_sv support

* delete the rvv tests

* add rvv testcases

* delete rvv testcase again

* add rvv testcase for the next update

This reverts commit b0c5ed87.

  Time: 2022/2/25 13:08(Beijing)
  Commit id:a9e2ebe8
  For the preparations of open source RISC-V 'V' Features.

Use the Long Long Float wrapper in terms of Long Float for Alpha/Linux
targets as well, fixing gnatlib compilation errors:

a-nallfl.ads:48:13: warning: intrinsic binding type mismatch on result [enabledby default]
a-nallfl.ads:48:13: warning: intrinsic binding type mismatch on parameter 1 [enabled by default]
a-nallfl.ads:48:13: warning: profile of "Sin" doesn't match the builtin it binds [enabled by default]

etc. with the `alpha-linux-gnu' target.

	gcc/ada/
	PR ada/98724
	PR ada/97504
	* Makefile.rtl (LIBGNAT_TARGET_PAIRS) <alpha*-*-linux*>: Use
	wraplf version of Aux_Long_Long_Float.

It turns out to be painful to require linking against -lrt on
GNU/Linux, as that makes it harder to link Go code into C programs.
Instead just call the timer syscalls directly.  That is what the
upstream library does anyhow.

gcc/go/
	* gospec.cc: Revert 2022-02-09 change:
	(RTLIB, RT_LIBRARY): Don't define.
	(lang_specific_driver): Don't add -lrt if linking statically
	on GNU/Linux.

gotools/
	* configure.ac: Revert 2022-02-09 change:
	(RT_LIBS): Don't define.
	* Makefile.am (check-runtime): Don't set GOLIBS to $(RT_LIBS).
	* configure, Makefile.in: Regenerate.

Reviewed-on: https://go-review.googlesource.com/c/gofrontend/+/385475

Test case is https://go.dev/cl/385454.

Reviewed-on: https://go-review.googlesource.com/c/gofrontend/+/385474

PR104228 showed that character lengths were shared between associate
variable and associate targets.  This is problematic when the associate
target is itself a variable and gets a variable to hold the length, as
the length variable is added (and all the variables following it in the chain)
to both the associate variable scope and the target variable scope.
This caused an ICE when compiling with -O0 -fsanitize=address.

This change forces the creation of a separate character length for the
associate variable.  It also forces the initialization of the character
length variable to avoid regressing associate_32 and associate_47 tests.

	PR fortran/104228

gcc/fortran/ChangeLog:

	* resolve.cc (resolve_assoc_var): Also create a new character
	length for non-dummy associate targets.
	* trans-stmt.cc (trans_associate_var): Initialize character length
	even if no temporary is used for the associate variable.

gcc/testsuite/ChangeLog:

	* gfortran.dg/asan/associate_58.f90: New test.
	* gfortran.dg/asan/associate_59.f90: New test.

The pattern converts (cond (cmp a b) (convert c) (convert d))
to (convert (cond (cmp a b) c d)) when
1) types_match (c, d)
2) single_use for (convert c) and (convert d)
3) TYPE_PRECISION (TREE_TYPE (c)) == TYPE_PRECISION (TREE_TYPE (a))
4) INTEGERAL_TYPE_P (TREE_TYPE (c))

The pattern can save packing of mask and data(partial for data, 2 vs
1).

gcc/ChangeLog:

	PR target/103771
	* match.pd (cond_expr_convert_p): New match.
	* tree-vect-patterns.cc (gimple_cond_expr_convert_p): Declare.
	(vect_recog_cond_expr_convert_pattern): New.

gcc/testsuite/ChangeLog:

	* gcc.target/i386/pr103771-2.c: New test.
	* gcc.target/i386/pr103771-3.c: New test.

With -fstack-check* __builtin_alloca* can throw and the asan
instrumentation of this builtin wasn't prepared for that case.
The following patch fixes that by replacing the builtin with the
replacement builtin and emitting any further insns on the fallthru
edge.

I haven't touched the hwasan code which most likely suffers from the
same problem.

2022-02-12  Jakub Jelinek  <jakub@redhat.com>

	PR sanitizer/104449
	* asan.cc: Include tree-eh.h.
	(handle_builtin_alloca): Handle the case when __builtin_alloca or
	__builtin_alloca_with_align can throw.

	* gcc.dg/asan/pr104449.c: New test.
	* g++.dg/asan/pr104449.C: New test.

1. Require linker with GNU_PROPERTY_1_NEEDED support for PR 35513
run-time tests.
2. Compile pr35513-8.c to scan assembly code.

	PR testsuite/104481
	* g++.target/i386/pr35513-1.C: Require property_1_needed target.
	* g++.target/i386/pr35513-2.C: Likewise.
	* gcc.target/i386/pr35513-8.c: Change to compile.
	* lib/target-supports.exp (check_compile): Support assembly code.
	(check_effective_target_property_1_needed): New proc.

The following testcase ICEs, because AVX512F is enabled, AVX512VL is not,
and the cvtsd2ss insn has %xmm0-15 as output operand and %xmm16-31 as
input operand.  For output operand %xmm16+ the splitter just gives up
in such case, but for such input it just emits vmovddup which requires
AVX512VL if either operand is EXT_REX_SSE_REG_P (when it is 128-bit).

The following patch fixes it by treating that case like the pre-SSE3
output != input case - move the input to output and do everything on
the output reg which is known to be < %xmm16.

2022-02-12  Jakub Jelinek  <jakub@redhat.com>

	PR target/104502
	* config/i386/i386.md (cvtsd2ss splitter): If operands[1] is xmm16+
	and AVX512VL isn't available, move operands[1] to operands[0] first.

	* gcc.target/i386/pr104502.c: New test.

2022-02-12  Uroš Bizjak  <ubizjak@gmail.com>

gcc/ChangeLog:

	PR target/79754
	* config/i386/i386.cc (type_natural_mode):
	Skip decimal float vector modes.

gcc/testsuite/ChangeLog:

	PR target/79754
	* gcc.target/i386/pr79754.c: New test.

Two issues resulted in this PR, which manifests when we force a constant into
memory in LRA (in PIC code on Darwin).  The presence of such forced constants
is quite dependent on other RTL optimisations, and it is easy for the issue to
become latent for a specific case.

First, in the Darwin-specific rs6000 backend code, we were not being careful
enough in rejecting invalid symbolic addresses.  Specifically, when generating
PIC code, we require a SYMBOL_REF to be wrapped in an UNSPEC_MACHOPIC_OFFSET.

Second, LRA was attempting to load a register using an invalid lo_sum address.

Signed-off-by: Iain Sandoe <iain@sandoe.co.uk>
Co-authored-by: Vladimir Makarov <vmakarov@redhat.com>

	PR target/104117

gcc/ChangeLog:

	* config/rs6000/rs6000.cc (darwin_rs6000_legitimate_lo_sum_const_p):
	Check for UNSPEC_MACHOPIC_OFFSET wrappers on symbolic addresses when
	emitting PIC code.
	(legitimate_lo_sum_address_p): Likewise.
	* lra-constraints.cc (process_address_1): Do not attempt to emit a reg
	load from an invalid lo_sum address.

gcc/po/
	* gcc.pot: Regenerate.

libcpp/po/
	* cpplib.pot: Regenerate.

The logic in libcpp/Makefile.in listing diagnostic functions in a call
to xgettext was missing cpp_warning_at, cpp_pedwarning_at and
cpp_error_at, so resulting in some messages not being extracted for
translation; add those functions to those for which messages are
extracted.

Tested with "make cpplib.pot".

	* Makefile.in (po/$(PACKAGE).pot): Also handle cpp_warning_at,
	cpp_pedwarning_at and cpp_error_at.

The move of source files to .cc names broke most message extraction by
exgettext because it processed .c files with --language=GCC-source but
didn't process .cc files that way.  Fix to process files identified as
C++ that way as well.

Tested with "make gcc.pot".

	* exgettext: Also process C++ sources with --language=GCC-source.

gotools/
	* Makefile.am (go_cmd_cgo_files): Add ast_go118.go
	(check-go-tool): Copy golang.org/x/tools directories.
	* Makefile.in: Regenerate.

Reviewed-on: https://go-review.googlesource.com/c/gofrontend/+/384695

The std::get_temporary_buffer function is deprecated since C++17, but
the test was expecting a warning for C++14 as well.

libstdc++-v3/ChangeLog:

	* testsuite/20_util/temporary_buffer.cc: Fix dg-warning target
	selector.

libstdc++-v3/ChangeLog:

	* testsuite/20_util/monotonic_buffer_resource/allocate.cc:
	Ignore -Walloc-larger-than warning.
	* testsuite/20_util/unsynchronized_pool_resource/allocate.cc:
	Likewise.
	* testsuite/29_atomics/atomic/cons/user_pod.cc: Compile with -O1
	to avoid linker error for __atomic_is_lock_free.

The following testcase ICEs on x86_64-linux, because match.pd emits
there a NOP_EXPR cast from int*8 vector type with BLKmode to
unsigned*8 vector type with BLKmode and vec-lowering isn't prepared
to handle such casts.

Fixed by using VIEW_CONVERT_EXPR instead.

2022-02-11  Jakub Jelinek  <jakub@redhat.com>

	PR tree-optimization/104499
	* match.pd ((X & Y) CMP 0 -> X CMP2 ~Y): Use view_convert instead
	of convert.

	* gcc.c-torture/compile/pr104499.c: New test.

When looking at __builtin_clear_padding today, I've noticed that
it is quite wasteful to extend the original user one argument to 3,
2 is enough.  We need to encode the original type of the first argument
because pointer conversions are useless in GIMPLE, and we need to record
a boolean whether it is for -ftrivial-auto-var-init=* or not.
But for recording the type we don't need the value (we've always used
zero) and for recording the boolean we don't need the type (we've always
used integer_type_node).
So, this patch merges the two into one.

2022-02-11  Jakub Jelinek  <jakub@redhat.com>

	* tree.cc (build_common_builtin_nodes): Fix up formatting in
	__builtin_clear_padding decl creation.
	* gimplify.cc (gimple_add_padding_init_for_auto_var): Encode
	for_auto_init in the value of 2nd BUILT_IN_CLEAR_PADDING
	argument rather than in 3rd argument.
	(gimplify_call_expr): Likewise.  Fix up comment formatting.
	* gimple-fold.cc (gimple_fold_builtin_clear_padding): Expect
	2 arguments instead of 3, take for_auto_init from the value
	of 2nd argument.

v850 target has an interesting insn alternative constraint 'e!r' where e
denotes even general regs and e is a subset of r.  We cannot just make
union of exclude start hard registers for e and r and should use only
exclude start hard registers of r.  The following patch implements this.

gcc/ChangeLog:

	PR rtl-optimization/104400
	* lra-constraints.cc (process_alt_operands): Don't make union of
	this_alternative_exclude_start_hard_regs when reg class in insn
	alternative covers other reg classes in the same alternative.

gcc/testsuite/ChangeLog:

	PR rtl-optimization/104400
	* gcc.target/v850/pr104400.c: New.
	* gcc.target/v850/v850.exp: New.