Commits · tutorial_demo · github.com / riscv-boom / rocket-chip

Jul 29, 2016
- Clean up tutorial demo code now that rocket-chip supports all the configurations · cb58066d
  Megan Wachs authored Jul 28, 2016
  
  cb58066d
- Merge remote-tracking branch 'origin/master' into new_tutorial_demo · 291488ec
  Megan Wachs authored Jul 28, 2016
  
  291488ec
Jul 27, 2016
- fix LRSC issue (fixes issue #86) · 9c89290e
  Howard Mao authored Jul 26, 2016
  
  9c89290e
- fix L2 deadlock bug and add more advanced trace generator · ecd1af32
  Howard Mao authored Jul 26, 2016
  
  ecd1af32
Jul 26, 2016
- make sure L1 and L2 agree on coherence policy · 1063d909
  Howard Mao authored Jul 25, 2016
  
  1063d909
Jul 23, 2016
- fix assembly tests for configurations without VMU and/or user mode · 6a5b2d7f
  Howard Mao authored Jul 22, 2016
  
  6a5b2d7f
Jul 22, 2016
- some fixes and cleanup to stateless bridge · 75347eed
  Howard Mao authored Jul 21, 2016
  
  75347eed
- If NTiles == 1, only use MEI. Also Create configuration for ManagerToClientStatelessBridge. · c31c650d
  Megan Wachs authored Jul 18, 2016
  
  c31c650d
- bump uncore for L2 bugfix · ffe17cbb
  Howard Mao authored Jul 21, 2016
  
  ffe17cbb
- generate more L1 voluntary releases in TraceGen · 20df74d1
  Howard Mao authored Jul 20, 2016
  
  20df74d1
Jul 20, 2016

rocket: support asynchronous external busses · 9ae23f18
Wesley W. Terpstra authored Jul 18, 2016

9ae23f18

Bug fixes in SimpleHellaCacheIF and L2 agents · 19b44ec9

Howard Mao authored Jul 19, 2016

 * SimpleHellaCacheIF now properly handles both the non-blocking data
   cache and blocking data cache.
 * SimpleHellaCacheIF maintains ordering of replayed requests
 * L2 VoluntaryReleaseTracker sends voluntary release grant properly
 * Coherence protocols now downgrade for probeCopy

19b44ec9

Jul 19, 2016
- switch groundtest to merged master · 39a1ecbf
  Howard Mao authored Jul 18, 2016
  
  39a1ecbf
Jul 17, 2016
- refactor groundtest unittests into separate package · e08ec42b
  Howard Mao authored Jul 14, 2016
  
  e08ec42b
Jul 16, 2016
- Rename MulDivUnroll to MulUnroll · 407bc95c
  Megan Wachs authored Jul 15, 2016
  
  407bc95c
- Create seperate Mul/Div paramters instead of UseFastMulDiv · 4c26a6bc
  Megan Wachs authored Jul 15, 2016
  
  4c26a6bc
Jul 15, 2016
- bump rocket · ba082554
  Andrew Waterman authored Jul 14, 2016
  
  ba082554
- Bump rocket; remove ICacheBufferWays parameter · 768403f8
  Andrew Waterman authored Jul 14, 2016
  
  768403f8
Jul 14, 2016
- remove unnecessary CAMs from converters · 18ea58c8
  Howard Mao authored Jul 13, 2016
  
  18ea58c8
Jul 13, 2016
- add a script for checking comparator trace · 4c79215f
  Howard Mao authored Jul 12, 2016
  
  4c79215f
Jul 12, 2016
- Add a few things necessary to build for the workshop tutorial · 78108195
  Megan Wachs authored Jul 12, 2016
  
  78108195
- make sure DirectGroundTest testers given correct TL settings · 90bcd3db
  Howard Mao authored Jul 11, 2016
  
  90bcd3db
- optionally export detailed status information in DirectGroundTest · 8f0fa11c
  Howard Mao authored Jul 11, 2016
  
  8f0fa11c
- make sure dramsim reads and writes occur in the order they are received · b64998ec
  Howard Mao authored Jul 11, 2016
  
  b64998ec
- allow direct instatiation of arbitrary non-caching groundtests · cb2a18b5
  Howard Mao authored Jul 11, 2016
  
  cb2a18b5
- add top that directly tests the TL -> AXI converters · f03ffb32
  Howard Mao authored Jul 08, 2016
  
  f03ffb32
- don't use splat and bug out if too many address map entries · b47f8fbc
  Howard Mao authored Jul 11, 2016
  
  b47f8fbc
- rocket: add an AXI master port into the chip · 46fc9744
  Wesley W. Terpstra authored Jul 05, 2016
  
  46fc9744
- ext: support multiple external AHB/AXI ports · 8ac7fa55
  Wesley W. Terpstra authored Jul 05, 2016
  
  8ac7fa55
Jul 11, 2016
- Update README.md (#161) · 36720d91
  mwachs5 authored Jul 11, 2016
```
Correct typo in heading
```
  36720d91
Jul 09, 2016
- Fix Verilator VCD (#157) · 9751ea0f
  Andrew Waterman authored Jul 09, 2016
  
  9751ea0f
- don't add io:ext region to address map if no external MMIO · 9ec55ebb
  Howard Mao authored Jul 08, 2016
  
  9ec55ebb
- allow NastiConverterTest and Memtest to run simultaneously · 35547aa4
  Howard Mao authored Jul 08, 2016
  
  35547aa4
- refactoring groundtest configuration · 35866869
  Howard Mao authored Jul 08, 2016
  
  35866869
- get rid of TL -> AXI buffering and fix SimpleHellaCacheIF for non-blocking DCache · eeac405e
  Howard Mao authored Jul 07, 2016
  
  eeac405e
Jul 08, 2016
- Fix testing of DefaultSmallConfig; bump rocket et al · 32ee5432
  Andrew Waterman authored Jul 07, 2016
  
  32ee5432
Jul 07, 2016
- add buffering and locking to TL -> AXI converter · 8c13e78a
  Howard Mao authored Jul 06, 2016
  
  8c13e78a
- fix voluntary release issue in L2 cache · e27cb5f8
  Howard Mao authored Jul 06, 2016
  
  e27cb5f8
- Update to new priv-1.9 PTE format · 2a146155
  Andrew Waterman authored Jul 06, 2016
  
  2a146155
Jul 06, 2016
- fix TraceGen and Nasti -> TL converter · f79a3285
  Howard Mao authored Jul 05, 2016
  
  f79a3285