Commits · tlregrouter-user-bits · github.com / riscv-boom / rocket-chip · GitLab

Nov 18, 2020
- tilelink: expose user bits to TLRegisterRouterNode · f988e012
  Henry Cook authored Nov 17, 2020
  
  f988e012
- Merge pull request #92 from sifive/tile-reset-crossing-type · 125d3b90
  Henry Cook authored Nov 17, 2020
```
Define ResetCrossingType and Avoid Subsystem Implicit Clock
```
  125d3b90
- tile: add backwards compatibility trace broadcast node · 9d29200a
  Henry Cook authored Nov 17, 2020
  
  9d29200a
- update imports based on scalafix after rebasing · f0f150d5
  Henry Cook authored Oct 28, 2020
  
  f0f150d5
- tile: use BundleBridgeBlockDuringReset for tile trace interfaces · fbf5c672
  Henry Cook authored Sep 28, 2020
  
  fbf5c672
- util: BlockableTraceCoreInterface · 127463dc
  Henry Cook authored Sep 28, 2020
  
  127463dc
- util: type class implicit Blockable · 7c00c582
  Henry Cook authored Sep 25, 2020
  
  7c00c582
- differentiate ClockCrossingHelpers from ResetCrossingHelpers · 50e35ec7
  Henry Cook authored Sep 18, 2020
  
  50e35ec7
- diplomacy & prci: adjust crossingtype locations and type hierarchy · 3aa89ffc
  Henry Cook authored Sep 18, 2020
  
  3aa89ffc
- tile: preserve bind query on slaveNode · bc1ca706
  Henry Cook authored Sep 16, 2020
  
  bc1ca706
- util: fix blockduringreset counter to saturate · 512a13fd
  Henry Cook authored Sep 16, 2020
  
  512a13fd
- Revert "Ensure trace.valid is 0 during async reset" · dda896eb
  Henry Cook authored Sep 16, 2020
```
This reverts commit e3d506da.
```
  dda896eb
- prci: add ResetCrossingType and use with CrossingHelpers to control BlockDuringReset presence · f3a75980
  Henry Cook authored Sep 16, 2020
  
  f3a75980
- diplomacy: CreditedCrossing implies same clock · 66eb8d58
  Henry Cook authored Sep 16, 2020
  
  66eb8d58
- block during reset supports blocking for a stretched amount of cycles · 0bcd4239
  Henry Cook authored Sep 14, 2020
  
  0bcd4239
- interrupts: IntTempNode · 9c52f661
  Henry Cook authored Sep 16, 2020
  
  9c52f661
- rational crossing: dont BlockDuringReset deq · 192660f9
  Henry Cook authored Sep 16, 2020
  
  192660f9
- prci: get more aggresive with shouldBeInlined for various adapters and wrappers · 90752cd2
  Henry Cook authored Sep 14, 2020
  
  90752cd2
- Expose control over take field for all ClockSinkParameters · 4bd5dbba
  Jerry Zhao authored Aug 24, 2020
  
  4bd5dbba
- prci: alternate clock domain constructors · 62c984bf
  Henry Cook authored Sep 11, 2020
  
  62c984bf
- tile: provide reset domain container · 1a403862
  Henry Cook authored Sep 11, 2020
```
intended to hold all BlockDuringReset components that need to be asynchronously reset
```
  1a403862
- update BlockDuringReset and add TL and Interrupt versions · 93d4a69f
  Henry Cook authored Sep 11, 2020
  
  93d4a69f
- Revert "Use unmodified, possibly async reset for notification ports" · 962a2a01
  Henry Cook authored Sep 08, 2020
```
This reverts commit 16329253.
```
  962a2a01
- Revert "Revise trace.valid gating method to relieve timing on reset" · 68a1541d
  Henry Cook authored Sep 08, 2020
```
This reverts commit ede4d59a.
```
  68a1541d
- Revert "Move beu interrupt crossing source register into Tile" · ccac2324
  Henry Cook authored Sep 08, 2020
```
This reverts commit c8f7e470.
```
  ccac2324
- Move beu interrupt crossing source register into Tile · 1fbe3b94
  Ernie Edgar authored Aug 30, 2020
  
  1fbe3b94
- [prci] Provide ibus clock from sbus in BaseSubsystem · 1182ff85
  David Biancolin authored Nov 13, 2020
  
  1182ff85
- Have InterruptBusWrapper extend ClockSinkDomain · 463e1f14
  David Biancolin authored Nov 12, 2020
  
  463e1f14
- [prci] Provide a require message for ClockGroupAggregator when in.size =/= 1 · 564e2371
  David Biancolin authored Nov 08, 2020
  
  564e2371
- Eschew use of subsystem implicit clock in CLINT · 67aecaa2
  David Biancolin authored Nov 08, 2020
  
  67aecaa2
- Eschew use of subsystem implicit clock in HasPeripheryDebug · 4c5cc87c
  David Biancolin authored Nov 08, 2020
  
  4c5cc87c
- Eschew use of subsystem implicit clock in PLIC + IntBus Wrapper · 77b551f0
  David Biancolin authored Nov 08, 2020
  
  77b551f0
- Eschew use of subsystem implicit clock in BootROM · 892ddb6d
  David Biancolin authored Nov 08, 2020
  
  892ddb6d
- Eschew use of subsystem implicit clock for RTC mixin · 35e167a4
  David Biancolin authored Nov 08, 2020
  
  35e167a4
Nov 17, 2020
- Merge pull request #87 from sifive/revert-86-revert-plic-priority-reg-change · d83350bf
  Megan Wachs authored Nov 16, 2020
```
Revert "Revert "Merge pull request #2718 from chipsalliance/plic-reg-descs""
```
  d83350bf
- Revert "Revert "Merge pull request #2718 from chipsalliance/plic-reg-descs" (#86)" · 72dd1932
  Megan Wachs authored Nov 16, 2020
```
This reverts commit 95f585e6.
```
  72dd1932
Nov 15, 2020
- Revert "Merge pull request #2718 from chipsalliance/plic-reg-descs" (#86) · 95f585e6
  Richard Xia authored Nov 14, 2020
```
This reverts commit b5d797a4, reversing
changes made to 71218bea.
```
  95f585e6
- Merge pull request #85 from sifive/wit-ignore · 5de43737
  Matthew Conolly authored Nov 14, 2020
```
Bump private repos
```
  5de43737
- Bump wit-manifest.json · 3009d4b2
  Matthew Conolly authored Nov 14, 2020
  
  3009d4b2
- Revert "remove wit-manifest.json" · 21e15c7b
  Matthew Conolly authored Nov 14, 2020
```
This reverts commit a6aed896.
```
  21e15c7b