Deprecate several legacy APIs

Bump Chisel and firrtl along 3.4.1.x

fix a ccover bug in I$

This modified `ccover` is guarded by `refill_done`, which will only cover the last beat corruption. This PR use `refillError` to fix this.

* un-deprecate TLMasterSlavePortParameters.supports*

* move expectsVipCheckerMaster/Slave into Monitor.scala from Parameters.scala

* remove TLMasterPortParameters.expectsVipChecker

* remove TLSlavePortParameters.expectsVipChecker

* TileLink Monitor.scala: addressHelper supports/emit Safe, not Fast (assumed address exists)

* TileLink Parameters.scala: unresolved feedback from PR (#2505)

* remove deprecated TLMasterParameters.supports*

Co-authored-by: Andrew Waterman <andrew@sifive.com>

* PTW.scala: enabling configurable L2 TLB (sets/ways)

* un-do SFENCE precise search

* L2TLB: valid/g arrays same dimensions as ram: Vec(nWays, nSets)

* coreParams.nL2TLBWays

Co-authored-by: Nikos Ch. Papadopoulos <ncpapad@cslab.ece.ntua.gr>

Fix minor issue in readme about adding code for Debug

D$: fix two noisy-drop performance bugs

d_address_inc is only valid when d.valid is true (or, more precisely, when
d.bits.opcode is valid).  So, we weren't unblocking the core on the most
optimal cycle in some cases.  This only seems to happen in practice with
noisy drops, since there d.bits.opcode is sometimes ReleaseAck, whereas
otherwise d.bits.opcode is almost always GrantData.

Not a correctness issue.

If the C-channel TSHR is occupied and we wish to evict a clean line,
just silently drop the line rather than waiting for the TSHR to become
available.  Otherwise, we'd stretch the miss latency.

Co-authored-by: Megan Wachs <megan@sifive.com>

Define ResetCrossingType and use with BlockDuringReset in TilePRCIDomain

Avoid Subsystem Implicit Clock

Uses of `TLRegisterRouter`, `TLRegModule`, `TLRegBundle` should be replaced with the single trait `HasTLControlRegMap`

PLIC Priority RegFieldDesc fix off-by-one