related to #2670

Use sbt-sriracha for fully SBT-managed source dependencies. They are
also toggleable via JVM System Properties: sbt.sourcemode and
sbt.workspace.

Update Makefiles and build rocketchip fat jar.

Support switching between source and published chisel3 and firrtl, test
in CI. Document this flow for bumping and describe impact of this flow
on IDE use.

* Restoring staged generator PRs (Reverting #2329)

This reverts commit e170f8f8.

* bumping chisel 3.2.x

Mainly to mention that chisel3 and firrtl should only be bumped to
stable branches

Co-authored-by: Megan Wachs <megan@sifive.com>

* Revert "updating README examples with Make changes (#2322)"

This reverts commit 875dcd3e.

* Revert "fixing aspect generation (#2309)"

This reverts commit bbeb2578.

* Revert "separate generator behavior into phases (#2274)"

This reverts commit 9d997506.

Correct link to diplomacy carvv paper.

It is the correct config filename. Clearer this way.

makefile rules to checkout and build using this hash.

This saves time and links to the blog for newcomers who keep banging
their head against the wall when they can't compile custom example
programs.

fpga-zynq is now deprecated, move reference to sifive/freedom.

src/main/scala/rocketchip/Configs.scala should be src/main/scala/subsystem/Configs.scala now

* Added emulator debugging with GDB documentation

This documents the process of debugging RISC-V programs against the GNU debugger with OpenOCD.
https://github.com/freechipsproject/rocket-chip/issues/1339

* Review 1 by Megan.

review 1

* The executable arg is a dummy arg when using RBB emulator

* testing programs on emulator + reducing size ideas

+ Pointed out that {more size --> more execution time} and a solution.
+ Separated simple programs execution and testing (step 2) of program debugging (step 3): To illustrate the fact that custom programs can be run on the emulator too not only the benchmarks.

* typo minor change

* Modifications

Added an example command of VCD output + log file generation
Rearranged VCD size idea into the part where I talk about executing/testing
Cleaned redundancies

* coreplex collapse: peripherals now in coreplex

* coreplex: better factoring of TLBusWrapper attachement points

* diplomacy: allow monitorless :*= and :=*

* rocket: don't connect monitors to tile tim slave ports

* rename chip package to system

* coreplex: only sbus has a splitter

* TLFragmenter: Continuing my spot battles on requires without explanatory strings

* pbus: toFixedWidthSingleBeatSlave

* tilelink: more verbose requires

* use the new system package for regression

* sbus: add more explicit FIFO attachment points

* delete leftover top-level utils

* cleanup ResetVector and RTC

also update list of files expected to be seen in generated-src

* Refactors package hierarchy.

Additionally:
  - Removes legacy ground tests and configs
  - Removes legacy bus protocol implementations
  - Removes NTiles
  - Adds devices package
  - Adds more functions to util package

As pointed out, if we just point to 'master' branch, then people wouldn't get the correct list of dependencies.

Tell people where to look to find package dependency information

Make it easier to build riscv-tools faster on multicore machines

As per https://github.com/ucb-bar/rocket-chip/pull/507

fixed torture link

Fixed path to Configs.scala

This is an unavoidably invasive commit, because it affects the unit tests
(which formerly exited using stop()), the test harness Verilog generator
(since it is no longer necessary), and the DRAM model (since it is no
longer connected).  However, this should substantially reduce the effort
of building test harnesses in the future, since manual or semi-automatic
Verilog writing should no longer be necessary.  Furthermore, there is now
very little duplication of effort between the Verilator and VCS test
harnesses.

This commit removes support for DRAMsim, which is a bit of an unfortunate
consequence.  The main blocker is the lack of Verilog parameterization for
BlackBox.  It would be straightforward to revive DRAMsim once support for
that feature is added to Chisel and FIRRTL.  But that might not even be
necessary, as we move towards synthesizable DRAM models and FAME-1
transformations.