Commits · beu-interrupt-cdc-hcook · github.com / riscv-boom / rocket-chip · GitLab

Nov 18, 2020
- tile: add backwards compatibility trace broadcast node · d585e680
  Henry Cook authored Nov 17, 2020
  
  d585e680
Nov 14, 2020
- Merge remote-tracking branch 'origin/avoid-subsystem-implicit-clock' into beu-interrupt-cdc-hcook · dab765b1
  Henry Cook authored Nov 13, 2020
  
  dab765b1
- update imports based on scalafix after rebasing · 5c6d174c
  Henry Cook authored Oct 28, 2020
  
  5c6d174c
- tile: use BundleBridgeBlockDuringReset for tile trace interfaces · 2a7cc474
  Henry Cook authored Sep 28, 2020
  
  2a7cc474
- util: BlockableTraceCoreInterface · 80548215
  Henry Cook authored Sep 28, 2020
  
  80548215
- util: type class implicit Blockable · a8d37cf8
  Henry Cook authored Sep 25, 2020
  
  a8d37cf8
- differentiate ClockCrossingHelpers from ResetCrossingHelpers · 3fac6f74
  Henry Cook authored Sep 18, 2020
  
  3fac6f74
- diplomacy & prci: adjust crossingtype locations and type hierarchy · 564b15a5
  Henry Cook authored Sep 18, 2020
  
  564b15a5
- tile: preserve bind query on slaveNode · 5881c825
  Henry Cook authored Sep 16, 2020
  
  5881c825
- util: fix blockduringreset counter to saturate · 1deb82ed
  Henry Cook authored Sep 16, 2020
  
  1deb82ed
- Revert "Ensure trace.valid is 0 during async reset" · aa6e2940
  Henry Cook authored Sep 16, 2020
```
This reverts commit e3d506da.
```
  aa6e2940
- prci: add ResetCrossingType and use with CrossingHelpers to control BlockDuringReset presence · fd84f137
  Henry Cook authored Sep 16, 2020
  
  fd84f137
- diplomacy: CreditedCrossing implies same clock · 0f79434e
  Henry Cook authored Sep 16, 2020
  
  0f79434e
- block during reset supports blocking for a stretched amount of cycles · fdecc969
  Henry Cook authored Sep 14, 2020
  
  fdecc969
- interrupts: IntTempNode · 0e38f02c
  Henry Cook authored Sep 16, 2020
  
  0e38f02c
- rational crossing: dont BlockDuringReset deq · 68a92a15
  Henry Cook authored Sep 16, 2020
  
  68a92a15
- prci: get more aggresive with shouldBeInlined for various adapters and wrappers · fc557e56
  Henry Cook authored Sep 14, 2020
  
  fc557e56
- Expose control over take field for all ClockSinkParameters · 533feb0b
  Jerry Zhao authored Aug 24, 2020
  
  533feb0b
- prci: alternate clock domain constructors · 52f34491
  Henry Cook authored Sep 11, 2020
  
  52f34491
- tile: provide reset domain container · 183cdc62
  Henry Cook authored Sep 11, 2020
```
intended to hold all BlockDuringReset components that need to be asynchronously reset
```
  183cdc62
- update BlockDuringReset and add TL and Interrupt versions · 628a6a6d
  Henry Cook authored Sep 11, 2020
  
  628a6a6d
- Revert "Use unmodified, possibly async reset for notification ports" · d90a7249
  Henry Cook authored Sep 08, 2020
```
This reverts commit 16329253.
```
  d90a7249
- Revert "Revise trace.valid gating method to relieve timing on reset" · dfae3849
  Henry Cook authored Sep 08, 2020
```
This reverts commit ede4d59a.
```
  dfae3849
- Revert "Move beu interrupt crossing source register into Tile" · 54bb3e19
  Henry Cook authored Sep 08, 2020
```
This reverts commit c8f7e470.
```
  54bb3e19
- Move beu interrupt crossing source register into Tile · 68ff5ce7
  Ernie Edgar authored Aug 30, 2020
  
  68ff5ce7
- [prci] Provide ibus clock from sbus in BaseSubsystem · 06f39ae9
  David Biancolin authored Nov 13, 2020
  
  06f39ae9
- Merge pull request #2729 from chipsalliance/elaboration-artefacts-renames · 71218bea
  Henry Cook authored Nov 13, 2020
```
allow renames to multiple targets for MemoryPathToken
```
  71218bea
Nov 13, 2020
- NMI implementation (#2711) · 12da135d
  Ernie Edgar authored Nov 13, 2020
  
  12da135d
- Rocket updates for zfh (#2723) · 63b76488
  Kira Tsao authored Nov 13, 2020
  
  63b76488
- Merge pull request #2730 from chipsalliance/fix-pwr-vipt · 614f2fd8
  Andrew Waterman authored Nov 12, 2020
```
Fix regression introduced by 40749694 for M_PWR commands
```
  614f2fd8
- Fix regression introduced by 40749694 for M_PWR commands · 13171a49
  Andrew Waterman authored Nov 12, 2020
```
Partial writes to the same word were not hazard-checked properly for
VIPT caches with page size < way size.
```
  13171a49
- handle single ref case · 95cf1d92
  Albert Chen authored Nov 12, 2020
  
  95cf1d92
- allow renames to multiple targets for MemoryPathToken · 02fd8daf
  Albert Chen authored Nov 12, 2020
  
  02fd8daf
- Have InterruptBusWrapper extend ClockSinkDomain · e7809955
  David Biancolin authored Nov 12, 2020
  
  e7809955
Nov 12, 2020
- Merge pull request #2727 from chipsalliance/elaboration-artefacts-annotation · 923ec05e
  Albert Chen authored Nov 11, 2020
```
add ElaborationArtefactAnnotation
```
  923ec05e
- actually run scalafix · fda1670c
  Albert Chen authored Nov 11, 2020
  
  fda1670c
- run scalafix · 5884d392
  Albert Chen authored Nov 11, 2020
  
  5884d392
- Merge pull request #2725 from timsnyder-siv/create-targetdirkey · 0049f6ee
  Henry Cook authored Nov 11, 2020
```
Create TargetDirKey to expose Stage's --target-dir to Config
```
  0049f6ee
- add ElaborationArtefactAnnotation · 36a610ff
  Albert Chen authored Nov 11, 2020
  
  36a610ff
Nov 11, 2020
- Merge pull request #2724 from chipsalliance/bus-crossing-misc · 75c01f1b
  David Biancolin authored Nov 10, 2020
```
Add An Optional L2:MBus crossing; Misc Xtype + Bus Frequency Config Mixins
```
  75c01f1b