Commits · full-privilege · github.com / riscv-and-rust-and-decaf / riscv32i-cpu-chisel

Aug 02, 2018
- finish timeinterupt, use csr way to set mtimecmp · e302c135
  ommyzhang authored Aug 02, 2018
  
  e302c135
Aug 01, 2018
- Merge branch 'master' into full-privilege · 2d582e99
  ommyzhang authored Aug 01, 2018
  
  2d582e99
- time interrupt and fake external interrupt · 0af3a966
  ommyzhang authored Aug 01, 2018
  
  0af3a966
Jul 31, 2018
- sfence.vma · c308c8a3
  ommyzhang authored Jul 31, 2018
  
  c308c8a3
- Fix misa. Pass test `rv32mi-p-mcsr`. · 7605990a
  WangRunji authored Jul 31, 2018
  
  7605990a
- Handle jump target misaligned exception in ID. Pass test `rv32mi-p-ma_fetch`. · 6e2d3dc2
  WangRunji authored Jul 31, 2018
  
  6e2d3dc2
- Handle address misaligned exception & mtval. Pass test `rv32mi-p-ma_addr` · 9566a16f
  WangRunji authored Jul 31, 2018
  
  9566a16f
- Add tester for riscv-tests. Some passed, others did not. · 4a2ff687
  WangRunji authored Jul 31, 2018
  
  4a2ff687
- Fix ID B-inst compare bug. · f5850104
  WangRunji authored Jul 31, 2018
  
  f5850104
Jul 30, 2018
- Merge remote-tracking branch 'origin/master' · d725c65e
  WangRunji authored Jul 30, 2018
  
  d725c65e
- Fix CSR flush signal. Fix MEM test. · 4711ecd7
  WangRunji authored Jul 30, 2018
  
  4711ecd7
- fence and fence.i · 6ddb446d
  ommyzhang authored Jul 30, 2018
  
  6ddb446d
- Update riscv-prebuilt-toolchains · cf4681bc
  WangRunji authored Jul 30, 2018
  
  cf4681bc
- Add riscv-test cases. Add script to run qemu and trace. · daccdfac
  WangRunji authored Jul 30, 2018
  
  daccdfac
- Fix PTW. Pass page table test. · f594f37d
  WangRunji authored Jul 30, 2018
  
  f594f37d
- Optimize code. Modify CSR ... · 038ea69f
  WangRunji authored Jul 30, 2018
```
* Merge xRet to excep.
* Read prv at ID.
* epc no longer +4.
```
  038ea69f
- Fix missing SH op · eb498fb2
  WangRunji authored Jul 30, 2018
  
  eb498fb2
- Optimize code. Add valid flag from IF -> MEM. Fix PC trace. · 9b7e6991
  WangRunji authored Jul 30, 2018
  
  9b7e6991
- Optimize code. Move CSR calculation from EX to ID. · b67333bd
  WangRunji authored Jul 30, 2018
  
  b67333bd
Jul 29, 2018
- Add and test monitor. · 94d148d7
  WangRunji authored Jul 29, 2018
  
  94d148d7
- Detect invalid address and abort in IOManager · 3e7c1568
  WangRunji authored Jul 29, 2018
  
  3e7c1568
- Optimize CSR for vivado compiling. · 56e8fb98
  WangRunji authored Jul 29, 2018
  
  56e8fb98
- Fix ID bug again. Fix tester bug. · a3d01014
  WangRunji authored Jul 29, 2018
  
  a3d01014
- Fix merge bug in CSR · bd2778e1
  WangRunji authored Jul 29, 2018
  
  bd2778e1
- Merge remote-tracking branch 'origin/master' into mmu · 28c0063e
  WangRunji authored Jul 29, 2018
```
# Conflicts:
#	src/main/scala/core_/CSR.scala
#	src/main/scala/core_/MEM.scala
```
  28c0063e
- New test method: write x31 to indicate pass or fail. · fb7dfd67
  WangRunji authored Jul 29, 2018
  
  fb7dfd67
- Merge branch 'master' into full-privilege · 6ba0fba9
  ommyzhang authored Jul 29, 2018
  
  6ba0fba9
Jul 28, 2018
- MMU basically works! · 6ea49c56
  WangRunji authored Jul 28, 2018
  
  6ea49c56
- Page table test case · efa9734d
  WangRunji authored Jul 28, 2018
  
  efa9734d
- xRET pass test · 3db9915c
  ommyzhang authored Jul 28, 2018
  
  3db9915c
- finish xRet, change ECALL, and exception can stall in MEM · 1209b2be
  ommyzhang authored Jul 28, 2018
  
  1209b2be
- Finish MMU, not yet enabled and tested. · 0bb8c8d0
  WangRunji authored Jul 28, 2018
  
  0bb8c8d0
- Use Mem to store CSR. Add S-Mode CSRs. Add CSR_MMU interface. · 56f85b7f
  WangRunji authored Jul 28, 2018
  
  56f85b7f
- Simplify PTW interface · 3c08db84
  WangRunji authored Jul 28, 2018
  
  3c08db84
Jul 27, 2018
- Bundle Exception · 3f7f881d
  WangRunji authored Jul 27, 2018
  
  3f7f881d
- Add and use Cause consts · c81624c0
  WangRunji authored Jul 27, 2018
  
  c81624c0
- PTW no longer locks input, which makes it faster. · 3afef518
  WangRunji authored Jul 27, 2018
  
  3afef518
- Change TLB impl to direct mapping. · de21699a
  WangRunji authored Jul 27, 2018
  
  de21699a
- Rename PageTableWalker to PTW · e8e84062
  WangRunji authored Jul 27, 2018
  
  e8e84062
- Add another query port for TLB. Link TLB to MMU, but not enabled. · 3f5cbd2b
  WangRunji authored Jul 27, 2018
  
  3f5cbd2b