Commit 5291fe3c authored by Srinath Parvathaneni's avatar Srinath Parvathaneni
Browse files

aarch64: Add support for bfloat16 in gdb.

This patch adds support for bfloat16 in AArch64 gdb.
Also adds the field "bf" to vector registers h0-h31.
Also adds the vector "bf" to h field in vector registers v0-v31.

The following is how the vector register h and v looks like.

Before this patch:
(gdb) p $h0
$1 = {f = 0, u = 0, s = 0}
(gdb) p/x $h0
$2 = {f = 0x0, u = 0x0, s = 0x0}
(gdb) p $v0.h
$3 = {f = {0, 0, 0, 0, 0, 0, 0, 0}, u = {0, 0, 0, 0, 0, 0, 0, 0}, s = {0, 0, 0, 0, 0, 0, 0, 0}}
(gdb) p/x $v0.h
$4 = {f = {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, u = {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},
      s = {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}

After this patch:
(gdb) p $h0
$1 = {bf = 0, f = 0, u = 0, s = 0}
(gdb) p/x $h0
$2 = {bf = 0x0, f = 0x0, u = 0x0, s = 0x0}
(gdb) p $v0.h
$3 = {bf = {0, 0, 0, 0, 0, 0, 0, 0}, f = {0, 0, 0, 0, 0, 0, 0, 0}, u = {0, 0, 0, 0, 0, 0, 0, 0},
      s = {0, 0, 0, 0, 0, 0, 0, 0}}
(gdb) p/x $v0.h
$4 = {bf = {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, f = {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},
      u = {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, s = {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}

gdb/ChangeLog:

2021-01-12  Srinath Parvathaneni  <srinath.parvathaneni@arm.com>

	* aarch64-tdep.c (aarch64_vnh_type): Add "bf" field in h registers.
	(aarch64_vnv_type): Add "bf" type in h field of v registers.
	* features/aarch64-fpu.c (create_feature_aarch64_fpu): Regenerated.
	* features/aarch64-fpu.xml: Add bfloat16 type.

gdb/testsuite/ChangeLog:

2021-01-12  Srinath Parvathaneni  <srinath.parvathaneni@arm.com>

	* gdb.arch/aarch64-fp.exp: Modify to test bfloat16 support.
parent d546b610
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