gdb/aarch64: Add named flags for FPCR and FPSR registers

This patch updates FPCR (Floating-point Control Register) and FPSR
(Floating-point Status Register) named fields in AArch64. For detailed
description of named register FPCR and FPSR bit fields see [1] and [2].

Please not that bit fields FIZ, AH and NEP (bits 0, 1 and 2 respectively) in
FPCR are defined starting from Armv8.7 architecture.

[1]: https://developer.arm.com/docs/ddi0595/i/aarch64-system-registers/fpcr
[2]: https://developer.arm.com/docs/ddi0595/i/aarch64-system-registers/fpsr

Example:
>>> info all-registers fpsr
fpsr           0x10                [ IXC ]
>>> info all-registers fpcr
fpcr           0x0                 [ RMode=0 ]