CV32E40Pv2 220 CORE-V SIMD Builtins Version 1

    * gcc/config/riscv/constraints.md: Created
        * 6-bit signed immediate constraint "CV6"
        * 6-bit unsigned immediate constraint "CS6"
        * 1-bit shifting immediate constraint:
          * constant integer value "0" constraint "CF0"
          * constant integer value "1" constraint "CF1"
          * constant integer value "2" constraint "CF2"
          * constant integer value "3" constraint "CF3"

    * gcc/config/riscv/corev.def: Defined 142 SIMD builtins
      for 220 SIMD instructions with RISCV_BUILTIN.

    * gcc/config/riscv/corev.md:
      * Machine description pattern for all 142 SIMD builtins with
        UNSPEC version.
      * Included `define_c_enum "unspec"` for CORE-V specific
        unspec macros.

    * gcc/config/riscv/predicates.md: Created
        * 6-bit signed immediate predicate for constraint "CV6"
        * 6-bit unsigned immediate predicate for constraint "CS6"
        * 4-bit unsigned immediate predicate for constraint
          "CF0,CF1,CF2,CF3"

    * gcc/config/riscv/riscv-builtins.cc: Created SIMD Avaliability
      Predicate, RISCV_FTYPE_NAME2, RISCV_FTYPE_ATYPES2. Added
      corresponding argument types for builtins.

    * gcc/config/riscv/riscv-ftypes.def: Added corresponding
      DEF_RISCV_FTYPE return type and argument types for builtins.