Commit b34f9d1c authored by Jeremy Bennett's avatar Jeremy Bennett
Browse files

Update CORE-V documentation.



	* doc/extend.texi (CORE-V Builtin-in Functions): Rename as RISC-V
	(CORE-V), provide sub-subsection for the builtins for each ISA
	extension, present builtins as simple lists, reorder ISA
	extensions alphabetically.
	* doc/invoke.texi (RISC-V Options): Add missing CORE-V options for
	-march and order those options alphabetically.

Signed-off-by: default avatarJeremy Bennett <jeremy.bennett@embecosm.com>
parent d2593267
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