Fixes to xcvbitmanip and xcvsimd

The immediate operand order in instructions `cv.bclr` and `cv.bset`
was wrong. Tests updated to match.

Tests for instructions `cv.extract[u].[h,b]` and `cv.insert.[h,b]`
fixed for unsigned immediate `sel`.

Instructions `cv.s[ll,ra,la].sc.[h,b]` fixed for unsigned immediate
`j`. Tests updated to match.

Files Changed:

  * config/riscv/corev.md: Various fixes.
  * gcc.target/riscv/cv-march-xcvbitmanip-compile-bclr.c: Fixed test.
  * gcc.target/riscv/cv-march-xcvbitmanip-compile-bset.c: Likewise.
  * gcc.target/riscv/cv-simd-extract-b-compile-1.c: Likewise.
  * gcc.target/riscv/cv-simd-extract-h-compile-1.c: Likewise.
  * gcc.target/riscv/cv-simd-extractu-b-compile-1.c: Likewise.
  * gcc.target/riscv/cv-simd-extractu-h-compile-1.c: Likewise.
  * gcc.target/riscv/cv-simd-insert-b-compile-1.c: Likewise.
  * gcc.target/riscv/cv-simd-insert-h-compile-1.c: Likewise.
  * gcc.target/riscv/cv-simd-sll-sc-b-compile-1.c: Likewise.
  * gcc.target/riscv/cv-simd-sll-sc-h-compile-1.c: Likewise.
  * gcc.target/riscv/cv-simd-sra-sc-b-compile-1.c: Likewise.
  * gcc.target/riscv/cv-simd-sra-sc-h-compile-1.c: Likewise.
  * gcc.target/riscv/cv-simd-srl-sc-b-compile-1.c: Likewise.
  * gcc.target/riscv/cv-simd-srl-sc-h-compile-1.c: Likewise.

Signed-off-by: Mary Bennett <mary.bennett@embecosm.com>