CV32E40Pv2 Event Load Builtin

	* gcc/common/config/riscv/riscv-common.cc: Added XCOREV and
	  XCOREVELW extensions. Added riscv_xcorev_flags to extensions.
	* gcc/config/riscv/corev.def: Implemented builtin prototype.
	* gcc/config/riscv/riscv-builtins.cc: Added AVAIL for XCOREVELW.
	  Declared pointer type node for builtin argument type.
	  Included "corev.def" to riscv_builtin_description
	  riscv_builtins[].
	* gcc/config/riscv/riscv-ftypes.def: Added DEF_RISCV_TYPE to
	  return an USI (unsigned integer) and take in a VOID_PTR
	  (void pointer).
	* gcc/config/riscv/riscv-opts.h: Added corresponding MASK and
	  TARGET macros for XCOREV and XCOREVELW.
	* gcc/config/riscv/riscv.md: Added machine description for cv.elw.
	* gcc/config/riscv/riscv.opt: Added Target Variable:
	  riscv_xcorev_flags.
	* gcc/testsuite/gcc.target/riscv/cv-elw-compile-1.c: Created test
	  for cv.elw builtin.

Signed-off-by: Nandni Jamnadas <nandni.jamnadas@embecosm.com>