RISC-V: Enable compressible features when use ZC* extensions.

This patch enables the compressible features with ZC* extensions.

Since all ZC* extension depends on the Zca extension, it's sufficient to only
add the target Zca to extend the target RVC.

Co-Authored by: Nandni Jamnadas <nandni.jamnadas@embecosm.com>
Co-Authored by: Simon Cook <simon.cook@embecosm.com>

gcc/ChangeLog:

        * config/riscv/riscv-c.cc (riscv_cpu_cpp_builtins):
	  Enable compressed builtins when ZC* extensions enabled.
        * config/riscv/riscv-shorten-memrefs.cc:
	  Enable shorten_memrefs pass when ZC* extensions enabled.
        * config/riscv/riscv.cc (riscv_compressed_reg_p):
	  Enable compressible registers when ZC* extensions enabled.
        (riscv_rtx_costs):
	  Allow adjusting rtx costs when ZC* extensions enabled.
        (riscv_address_cost):
	  Allow adjusting address cost when ZC* extensions enabled.
        (riscv_first_stack_step):
	  Allow compression of the register saves without
	  adding extra instructions.
        * config/riscv/riscv.h (FUNCTION_BOUNDARY):
	  Adjusts function boundary to 16 bits when ZC* extensions enabled.