Update operand order to match spec for bit manip instructions

Fix to issue #32.

gcc/config/riscv:
  * corev.md: Changed operand order from rd,rs1,Is3,Is2 to
    rd,rs1,Is2,Is3 for cv.bset, cv.bclr, cv.insert, cv.extractu,
    and cv.extract. This now matches the specification.

gcc/testsuite/gcc.target/riscv:
  * cv-march-xcvbitmanip-compile-bclr.c: Updated test to match spec.
  * cv-march-xcvbitmanip-compile-bset.c: Likewise.
  * cv-march-xcvbitmanip-compile-extract.c: Likewise.
  * cv-march-xcvbitmanip-compile-extractu.c: Likewise.
  * cv-march-xcvbitmanip-compile-insert.c: Likewise.